Multi-processor architecture using multiple switch fabrics implementing point-to-point serial links and method of operating same

• US 8,856,421 B2
• Filed: 12/14/2012
• Issued: 10/07/2014
• Est. Priority Date: 07/10/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Hamadani, Mehrdad, Bansal, Deepak, Moy, Sam Htin, Malli, Steenivasulu, Cheung, David, Kancherla, Mani, Devarapalli, Sridhar
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US13/715,674
• Publication Number:
  US 20130103881A1
• Time in Patent Office: 662 Days
• Field of Search: 710306-317, 710 36- 42, 709238-239
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.

Claims

1. A multi-processor architecture comprising:

a plurality of blades, each including;

a plurality of processors, a switch fabric that implements connections using point-to-point serial links, wherein the switch fabric is coupled to each of the plurality of processors, and packet processing logic coupled to the switch fabric;

a first external switch fabric that implements connections using point-to-point serial links, wherein the first external switch fabric is coupled to each switch fabric of the plurality of blades; and

a management processor coupled to the first external switch fabric.

2. The multi-processor architecture of claim 1, further comprising a processor accelerator coupled to the first external switch fabric.

3. The multi-processor architecture of claim 1, wherein the switch fabric of each of the blades comprises a PCI-Express (PCIe) switch.

4. The multi-processor architecture of claim 1, wherein each of the processors is a multi-core processor.

5. The multi-processor architecture of claim 1, wherein each of the processors is coupled to the switch fabric on the same blade by a plurality of point-to-point serial links.

6. The multi-processor architecture of claim 3, wherein the first external switch fabric comprises a PCI-Express (PCIe) switch.

7. A multi-processor architecture comprising:

a plurality of blades, each including;

a plurality of processors, a switch fabric that implements connections using point-to-point serial links, wherein the switch fabric is coupled to each of the plurality of processors, and packet processing logic coupled to the switch fabric;

a first external switch fabric that implements connections using point-to-point serial links, wherein the first external switch fabric is coupled to each switch fabric of the plurality of blades;

one or more line cards that receive and transmit data packets; and

a second external switch fabric coupling each of the one or more line cards to the packet processing logic of each of the plurality of blades.

8. The multi-processor architecture of claim 7, further comprising a third external switch fabric coupled to the first external switch fabric, the one or more line cards and the second external switch fabric, wherein the third external switch fabric implements connections using point-to-point serial links.

9. A method comprising:

routing a first packet from one of a first plurality of processors through a first switch fabric that implements connections using point-to-point serial links, wherein each of the first plurality of processors and the first switch fabric are located on a first blade;

routing a second packet from one of a second plurality of processors through a second switch fabric that implements connections using point-to-point serial links, wherein each of the second plurality of processors and the second switch fabric are located on a second blade;

routing the first packet from the first switch fabric and the second packet from the second switch packet through an external switch fabric that implements connections using point-to-point serial links; and

routing the first packet through the external switch fabric to a management processor.

10. The method of claim 9, further comprising routing the second packet through the external switch fabric to the management processor.

11. The method of claim 9, further comprising controlling operations of the first and second blades with the management processor.

12. The method of claim 9, further comprising routing the second packet through the external switch fabric to a processor accelerator.

13. A method comprising:

routing a first packet from one of a first plurality of processors through a first switch fabric that implements connections using point-to-point serial links, wherein each of the first plurality of processors and the first switch fabric are located on a first blade;

routing a second packet from one of a second plurality of processors through a second switch fabric that implements connections using point-to-point serial links, wherein each of the second plurality of processors and the second switch fabric are located on a second blade;

routing the first packet from the first switch fabric and the second packet from the second switch packet through an external switch fabric that implements connections using point-to-point serial links; and

routing the first packet through the external switch fabric to a processor accelerator.

14. The method of claim 13, further comprising performing a function with the processor accelerator in response to the first packet, thereby reducing processing requirements of the one of the first plurality of processors.

15. A multi-processor architecture comprising:

a first plurality of processors;

a first switch fabric that implements connections with point-to-point serial links, wherein the first plurality of processors are coupled to the first switch fabric by a first set of point-to-point serial links;

a second plurality of processors;

a second switch fabric that implements connections with point-to-point serial links, wherein the second plurality of processor are coupled to the first switch fabric by a second set of point-to-point serial links;

a third switch fabric that implements connections with point-to-point serial links, wherein the third switch fabric is coupled to the first switch fabric and the second switch fabric by a third set of point-to-point serial links; and

a management processor coupled to the third switch fabric.

16. The multi-processor architecture of claim 15,

wherein the first plurality of processors and the first switch fabric are located on a first blade, and the second plurality of processors and the second switch fabric are located on a second blade.

17. The multi-processor architecture of claim 16, wherein the third switch fabric is located external to the first blade and the second blade.