Memory controller and non-volatile storage device

• US 8,856,427 B2
• Filed: 03/30/2012
• Issued: 10/07/2014
• Est. Priority Date: 06/08/2011
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: So, Hirokazu, Honda, Toshiyuki
• Primary Examiner(s): Blair, April Y
• Assistant Examiner(s): TA, TRANG KHANH
• Application Number:
  US13/435,493
• Publication Number:
  US 20120317340A1
• Time in Patent Office: 921 Days
• Field of Search: 711/103, 711/193
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A non-volatile storage device comprises non-volatile memories for storing data; and a memory controller for carrying out control of the non-volatile memory. The memory controller stores second error correcting code as well as first error correcting code stored in the same page of the data. The memory controller, when writing data smaller than a predefined size, does not add the second error correcting code, and stores duplexed data of the data and the first correcting code in a different page. The memory controller, when reading, corrects data using the first and/or second correcting code. The valid data management table manages which logical block stores valid data with respect to an identical logical address.

Claims

1. A non-volatile storage device, which communicates with an access device and carries out reading and/or writing of data in accordance with a command from the access device, the non-volatile storage device comprising:

a non-volatile memory for storing data; and

a memory controller for carrying out control of the non-volatile memory,

wherein the non-volatile memory includes a plurality of blocks, which are erase units, each block of the plurality of blocks including a plurality of pages, which are write units of data, and

wherein the memory controller;

arranges a first logical block in one region by combining first blocks of the plurality of blocks, and arranges a second logical block in a different region by combining second blocks of the plurality of blocks;

assigns a plurality of error correcting groups to the first logical block, each error correcting group of the plurality of error correcting groups being configured by a plurality of pages of the first blocks of the first logical block;

assigns data and assigns at least one of a first error correcting code and a second error correcting code with respect to the data to each error correcting group;

configures one error correcting group of the plurality of error correcting groups as a parity group, the parity group including (i) data pages, of the first blocks of the first logical block, each of which includes the data and the first error correcting code with respect to the data and (ii) a parity page of one first block of the first logical block that includes the second error correcting code;

assigns a plurality of multiplexed groups to the second logical block, each multiplexed group of the plurality of multiplexed groups being configured by a plurality of data pages, each data page, of the second blocks of the second logical block, including data and the first error correcting code with respect to the data, and each multiplexed group of the plurality of multiplexed groups including one data page and a copy of the one data page as a copied data page;

when a data size of write data is smaller than a predetermined size, generates one data page from the write data and writes the generated data page and a copy of the generated data page as the copied data page in one multiplexed group to the second logical block, and when the data size of the write data is greater than or equal to the predetermined size, generates data pages and one parity page of the generated data pages from the write data and writes the generated data pages and the one parity page of the generated data pages in one parity group to the first logical block; and

includes a valid data management table for managing which one of the first logical block and the second logical block stores valid data with respect to an identical logical address.

2. The non-volatile storage device according to claim 1, wherein a size of a logical address space configured by the second logical block is smaller than a size of a logical address space configured by the first logical block.

3. The non-volatile storage device according to claim 1, wherein a number of blocks configuring the first logical block is equal to a number of blocks configuring the second logical block.

4. The non-volatile storage device according to claim 1, wherein:

the non-volatile memory is a flash memory capable of storing information exceeding a binary for every cell; and

at least the writing to the second blocks configuring the second logical block stores only information up to the binary for every cell.

5. The non-volatile storage device according to claim 1, wherein the memory controller:

makes one determination to write data to the second logical block when a data size of the data is smaller than a predetermined size, or makes another determination to write data to the first logical block when the data size of the data is greater than or equal to the predetermined size when writing data; and

writes the data based on the one determination or the other determination.

6. The non-volatile storage device according to claim 1, wherein each multiplexed group of the plurality of multiplexed groups is assigned data pages, of only two blocks of the second blocks of the second logical block, that each includes the data and the first error correcting code with respect to the relevant data.

7. The non-volatile storage device according to claim 1, wherein each multiplexed group of the plurality of multiplexed groups is configured by a plurality of data pages of the second blocks of the second logical block, and each multiplexed group of the plurality of multiplexed groups includes one data page of one second block of the second blocks and the copy of the one data page as the copied data page of another second block of the second blocks.

8. A memory controller for carrying out control of a non-volatile memory for storing data,

wherein the non-volatile memory includes a plurality of blocks, which are erase units, each block of the plurality of blocks including a plurality of pages, which are write units of data, and

wherein the memory controller:

arranges a first logical block in one region by combining first blocks of the plurality of blocks, and arranges a second logical block in a different region by combining second blocks of the plurality of blocks;

assigns a plurality of error correcting groups to the first logical block, each error correcting group of the plurality of error correcting groups being configured by a plurality of pages of the first blocks of the first logical block;

assigns data and assigns at least one of a first error correcting code and second error correcting code with respect to the data to each error correcting group;

configures one error correcting group of the plurality of error correcting groups as a parity group, the parity group including (i) data pages, of the first blocks of the first logical block, each of which includes the data and the first error correcting code with respect to the data and (ii) a parity page of one first block of the first logical block that includes the second error correcting code;

assigns a plurality of multiplexed groups to the second logical block, each multiplexed group of the plurality of multiplexed groups being configured by a plurality of data pages, each data page, of the second blocks of the second logical block, including data and the first error correcting code with respect to the data, and each multiplexed group of the plurality of multiplexed groups including one data page and a copy of the one data page as a copied data page;

when a data size of write data is smaller than a predetermined size, generates one data page from the write data and writes the generated data page and a copy of the generated data page as the copied data page in one multiplexed group to the second logical block, and when the data size of the write data is greater than or equal to the predetermined size, generates data pages and one parity page of the generated data page from the write data and writes the generated data pages and the one parity page of the generated data pages in one parity group to the first logical block; and

includes a valid data management table for managing which one of the first logical block and the second logical block stores valid data with respect to an identical logical address.

9. The memory controller according to claim 8, wherein a size of a logical address space configured by the second logical block is smaller than a size of a logical address space configured by the first logical block.

10. The memory controller according to claim 8, wherein a number of blocks configuring the first logical block is equal to a number of blocks configuring the second logical block.

11. The memory controller according to claim 8, wherein:

the non-volatile memory is a flash memory that stores information exceeding a binary for every cell; and

at least the writing to the second blocks configuring the second logical block stores only information up to the binary for every cell.

12. The memory controller according to claim 8, wherein the memory controller:

makes one determination to write data to the second logical block when a data size of the data is smaller than a predetermined size, or makes another determination to write data to the first logical block when the data size of the data is greater than or equal to the predetermined size when writing data; and

writes the data based on the one determination or the other determination.

13. The memory controller according to claim 8, wherein each multiplexed group of the plurality of multiplexed groups is assigned data pages, of only two blocks of the second blocks of the second logical block, that each includes the data and the first error correcting code with respect to the relevant data.

14. The memory controller according to claim 8, wherein each multiplexed group of the plurality of multiplexed groups is configured by a plurality of data pages of the second blocks of the second logical block, and each multiplexed group of the plurality of multiplexed groups includes one data page of one second block of the second blocks and the copy of the one data page as the copied data page of another second block of the second blocks.