Integrated circuit allowing to test a power management unit based on or more conditions and configuring the plurality of pins to operate in normal and test mode

• US 8,856,559 B2
• Filed: 04/02/2012
• Issued: 10/07/2014
• Est. Priority Date: 08/17/2011
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Alarcon, Veronica, Kothari, Love, Guettaf, Amar, Thompson, Kerry
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Sampath, Gayathri
• Application Number:
  US13/437,675
• Publication Number:
  US 20130047000A1
• Time in Patent Office: 918 Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

An integrated circuit is disclosed that contains both a PMU and another processing portion, such as a baseband. Because of the limited pins devoted to the PMU, the PMU receives most of its signals through the other processing portion of the integrated circuit. Thus, in order to protect the PMU, the integrated circuit isolates the PMU portion from receiving different signals from the other processing portion until after certain conditions are satisfied. In addition, the integrated circuit includes a GPIO pin bank in the other processing portion that can be freely configured so as to allow for testing of the PMU.

Claims

1. An integrated circuit that is included in a host electronic device, comprising:

a processor portion that includes;

a test mode input module configured to receive a test mode instruction signal from off-chip; and

an I/O module having a plurality of pins, configured to communicate with off-chip components; and

a power management portion configured to manage a power of the electronic device, the power management portion including;

a test module configured to set a test mode within the power management portion based on the test mode instruction signal received by the test mode input module,

wherein the test module is configured to output test result signals via the I/O module, and

wherein the plurality of pins provide a communication channel between the processor portion and the off-chip components during a normal mode of operation, and provide a communication channel between the power management portion and the off-chip components after the test mode has been set by the test module.

2. The integrated circuit of claim 1, wherein the test mode instruction signal is a Joint Test Action Group (JTAG) signal.

3. The integrated circuit of claim 1, wherein the plurality of pins of the I/O module are General Purpose Input/Output (GPIO) pins.

4. The integrated circuit of claim 3, wherein the power management portion configures the plurality of GPIO pins based on the set test mode.

19. The integrated circuit of claim 1, further comprising an isolation control module that defines an electrical boundary between the processor portion and the power management portion, the isolation control module configured to restrict access to the I/O module by the power management portion during the normal mode of operation, and to permit access to the I/O module by the power management portion after the test mode has been set provided that at least one condition has been met.

20. The integrated circuit of claim 19, wherein the isolation control module is further configured to prevent the test mode instruction signal received by the test mode input module to be received by the test module until the at least one condition has been met.

5. An integrated circuit that is included in a host electronic device, comprising:

a power management portion configured to manage a power of the electronic device;

a processor portion; and

an isolation control module configured to control an electrical isolation between the power management portion and the processor portion by restricting whether signals can be received by the power management module from the processor portion based on one or more conditions,

wherein the one or more conditions include whether a power start-up sequence is complete and whether the processor portion is receiving sufficient power.

6. The integrated circuit of claim 5, wherein the processor portion is a Baseband Processor.

7. The integrated circuit of claim 5, wherein the isolation control module includes a plurality of isolation gates that open or close based on the one or more conditions.

8. The integrated circuit of claim 5, wherein the power management portion includes a voltage detector module configured to detect a supply voltage supplied to the processor portion.

9. The integrated circuit of claim 8, wherein the isolation control module controls the electrical isolation of the power management portion from the processor portion based on the supply voltage detected by the voltage detector module.

10. The integrated circuit of claim 8, wherein the isolation control module isolates the power management portion from the processor portion when the supply voltage detected by the voltage detector module is below a predetermined threshold, and

wherein the isolation control module permits communication between the power management portion and the processor portion when the supply voltage detected by the voltage detector module is above the predetermined threshold.

11. The integrated circuit of claim 8, wherein the processor portion includes a test mode input module configured to receive a test mode signal for input to the integrated circuit.

12. The integrated circuit of claim 11, wherein the test mode signal is a Joint Test Action Group (JTAG) signal.

13. The integrated circuit of claim 11, wherein the isolation control module isolates the power management module from the test mode signal based on whether a power start-up sequence is complete, whether the supply voltage detected by the voltage detection module exceeds a predetermined threshold, and whether the test mode input module is receiving the test mode signal.

14. The integrated circuit of claim 11, wherein the power management portion includes a test module configured to receive the test mode signal from the test mode input module and to set a test mode based on the received test mode signal.

15. The integrated circuit of claim 11, wherein the processor portion includes an I/O module, and wherein the power management portion outputs test result signals via the I/O module.

16. The integrated circuit of claim 15, wherein the I/O module includes a plurality of General Purposes Input/Ouput (GPIO) pins.

17. The integrated circuit of claim 16, wherein the power management portion configures the plurality of GPIO pins based on the received test mode signal.

18. The integrated circuit of claim 11, wherein the isolation control module isolates the power management module from the test mode signal based on whether the supply voltage detected by the voltage detection module exceeds a predetermined threshold and whether the test mode input module is receiving the test mode signal, and regardless of whether a power start-up sequence is complete.