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Integrated circuit allowing to test a power management unit based on or more conditions and configuring the plurality of pins to operate in normal and test mode

  • US 8,856,559 B2
  • Filed: 04/02/2012
  • Issued: 10/07/2014
  • Est. Priority Date: 08/17/2011
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit that is included in a host electronic device, comprising:

  • a processor portion that includes;

    a test mode input module configured to receive a test mode instruction signal from off-chip; and

    an I/O module having a plurality of pins, configured to communicate with off-chip components; and

    a power management portion configured to manage a power of the electronic device, the power management portion including;

    a test module configured to set a test mode within the power management portion based on the test mode instruction signal received by the test mode input module,wherein the test module is configured to output test result signals via the I/O module, andwherein the plurality of pins provide a communication channel between the processor portion and the off-chip components during a normal mode of operation, and provide a communication channel between the power management portion and the off-chip components after the test mode has been set by the test module.

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