Information processing apparatus, control method, and computer-readable recording medium

• US 8,856,588 B2
• Filed: 08/29/2012
• Issued: 10/07/2014
• Est. Priority Date: 02/29/2012
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Koinuma, Hideyuki, Izui, Hiroyuki
• Primary Examiner(s): PATEL, KAMINI B
• Application Number:
  US13/597,428
• Publication Number:
  US 20130227224A1
• Time in Patent Office: 769 Days
• Field of Search: 714/6.1
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0817 using directory methods

Abstract

At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes.

Claims

1. An information processing apparatus comprising:

a plurality of nodes that each comprise a storage device; and

an interconnect that connects between the plurality of nodes,

wherein at least one node of the plurality of nodes comprises;

a detecting unit that detects a correctable error in data stored in a shared memory area included in a storage device of the one node or other node, the shared memory area being an area to which the one node and the other node access, and the correctable error being (i) an error which occurs more than a predetermined number of times within a predetermined time period or (ii) an error which occurs at a single location in the shared memory area;

a prevention control unit that, when the detecting unit detects the correctable error, performs control to prevent the one node and the other node from accessing the shared memory area by deleting, from first address converting information which associates a virtual address used for memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the one node, an entry which associates a virtual address with a physical address in the shared memory area in which the correctable error is detected and by transmitting, to the other node, an instruction to delete the entry from second address converting information which associates the virtual address used for the memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the other node;

a recovering unit that recovers the data stored in the shared memory area in a memory area different from the shared memory area;

a notifying unit that notifies information about the different memory area to the other node; and

a resumption control unit that performs control to resume the access to the recovered data from the one node and the other node.

2. The information processing apparatus according to claim 1, wherein the prevention control unit transmits to the other node an instruction for stopping an access to the shared memory from an application executed by the other node, and stops an access to the shared memory from an application executed by the one node.

3. The information processing apparatus according to claim 1, wherein the recovering unit acquires a page of other memory area to copy a page including the error of the shared memory area, and copies data stored in an area of the page including the error of the shared memory area to an area of the page of the other memory area.

4. The information processing apparatus according to claim 3, wherein the recovering unit divides the page of the shared memory area into a plurality of pages, and copies data stored in an area of a divided page including the error to an area of the page of the other memory area.

5. The information processing apparatus according to claim 4, wherein,

when the recovering unit divides the page of the shared memory area into the plurality of pages that have different sizes, the recovering unit includes the area of the divided page including the error into the divided page of a minimum size among the plurality of pages.

6. The information processing apparatus according to claim 3, wherein, when acquiring the page of the other memory area, if an acquirable page volume is a predetermined volume or less or acquisition of the page of the other memory area fails, the recovering unit divides the page of the shared memory area.

7. The information processing apparatus according to claim 3, wherein, when an OS (Operating System) is activated in a local node or an application using a shared memory of the local node or other node is activated, the recovering unit secures in advance an area of a predetermined size which can be used as the other memory area.

8. The information processing apparatus according to claim 1, wherein

the detecting unit detects a plurality of correctable errors, and

the prevention control unit performs the control to prevent the one node and the other node from accessing the shared memory area when an average value of an occurrence count of the plurality of correctable errors per unit time exceeds a threshold.

9. The information processing apparatus according to claim 8, wherein

the detecting unit detects a correctable error that occurs after a predetermined time from a final occurrence time of a previous correctable error as a first correctable error in the plurality of correctable errors.

10. An information processing apparatus comprising:

a plurality of nodes that each comprise a storage device; and

an interconnect that connects between the plurality of nodes,

wherein at least one node of the plurality of nodes comprises;

an access control unit that controls an access to the storage device of the one node, and comprises an error detecting unit that detects an error of data read from the storage device; and

a processing unit that performs a process comprising,

preventing an access to a shared memory area from the one node and other node by deleting, from first address converting information which associates a virtual address used for memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the one node, an entry which associates a virtual address with a physical address in the shared memory area in which a correctable error is detected and by transmitting, to the other node, an instruction to delete the entry from second address converting information which associates the virtual address used for the memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the other node, when the error detecting unit detects the correctable error of data stored in the shared memory area, the shared memory area being included in the storage device of the one node and accessed by the one node and the other node, the correctable error being (i) an error which occurs more than a predetermined number of times within a predetermined time period or (ii) an error which occurs at a single location in the shared memory area;

recovering the data stored in the shared memory area in a memory area different from the shared memory area and included in the storage device of the one node;

notifying information about the different memory area to the other node; and

resuming the access to the recovered data from the one node and the other node.

11. A non-transitory computer-readable recording medium having stored therein a control program for causing at least one node of a plurality of nodes in an information processing apparatus to execute a process, the information processing apparatus comprising the plurality of nodes each comprising a storage device, and an interconnect connecting between the plurality of nodes, the process comprising:

detecting a correctable error in data stored in a shared memory area included in a storage device of the one node or other node, the shared memory area being an area to which the one node and the other node access, and the correctable error being (i) an error which occurs more than a predetermined number of times within a predetermined time period or (ii) an error which occurs at a single location in the shared memory area;

when the correctable error is detected, performing control to prevent the one node and the other node from accessing the shared memory area by deleting, from first address converting information which associates a virtual address used for memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the one node, an entry which associates a virtual address with a physical address in the shared memory area in which the correctable error is detected and by transmitting, to the other node, an instruction to delete the entry from second address converting information which associates the virtual address used for the memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the other node;

recovering the data stored in the shared memory area in a memory area different from the shared memory area and included in the storage device of the one node;

notifying information about the different memory area to the other node; and

performing control to resume the access to the recovered data from the one node and the other node.

12. A control method performed by at least one node of a plurality of nodes in an information processing apparatus, the information processing apparatus comprising the plurality of nodes each comprising a storage device, and an interconnect connecting between the plurality of nodes, the control method comprising:

detecting a correctable error in data stored in a shared memory area included in a storage device of the one node or other node, the shared memory area being an area to which the one node and the other node access, and the correctable error being (i) an error which occurs more than a predetermined number of times within a predetermined time period or (ii) an error which occurs at a single location in the shared memory area;

when the correctable error is detected, performing control to prevent the one node and the other node from accessing the shared memory area by deleting, from first address converting information which associates a virtual address used for memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the one node, an entry which associates a virtual address with a physical address in the shared memory area in which the correctable error is detected and by transmitting, to the other node, an instruction to delete the entry from second address converting information which associates the virtual address used for the memory accesses of the one node and the other node with a physical address which indicates a data storing area in the storage device of the other node;

recovering the data stored in the shared memory area in a memory area different from the shared memory area;

notifying information about the different memory area to the other node; and

performing control to resume the access to the recovered data from the one node and the other node.