Method for generating post-OPC layout in consideration of top loss of etch mask layer

• US 8,856,695 B1
• Filed: 03/14/2013
• Issued: 10/07/2014
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Inventors: Han, Geng, Li, Wai-Kin, Chang, Sang Yil
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/829,054
• Publication Number:
  US 20140282297A1
• Time in Patent Office: 572 Days
• Field of Search: 716 52- 54, 716/56
• US Class Current: 716/54
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.

Claims

1. A method of forming a semiconductor circuit, comprising:

receiving target layout data using an apparatus;

performing an optical proximity correction process on the target layout data and generating post-OPC layout data therefrom;

performing a patterning process using the post-OPC layout data,

wherein the post-OPC layout data is adjusted to compensate for a top loss of an etch mask layer that occurs in an etching process that is performed using the etch mask layer;

calculating a threshold light amount of the etch mask layer, wherein the threshold light amount is selected to prevent the etch mask layer from being removed in the etching process; and

calculating a threshold background light intensity of the etch mask layer based on the threshold light amount, wherein the threshold background light intensity is a light intensity when the amount of background light that leaks from an exposed region of the etch mask layer to an unexposed region is substantially equal to the threshold light amount.

2. The method of claim 1, wherein the etch mask layer comprises a photoresist layer.

3. The method of claim 1, wherein performing the optical proximity correction process comprises adjusting the target layout data so that a background light intensity of at least a portion of the unexposed region separating two or more exposed regions of the etch mask layer is less than the threshold background light intensity.

4. The method of claim 1, wherein performing the optical proximity correction process comprises:

adjusting an edge of the target layout data;

calculating aerial image information based on the edge-adjusted target layout data;

determining whether the aerial image information satisfies the threshold background light intensity; and

classifying the edge-adjusted target layout data to be in a state of satisfying a litho-resist rule of the optical proximity correction process when the aerial image information satisfies the threshold background light intensity and classifying the edge-adjusted target layout data not to be in a state of satisfying the litho-resist rule of the optical proximity correction when the aerial image information does not satisfy the threshold background light intensity.

5. The method of claim 1, wherein performing the optical proximity correction process comprises adjusting the target layout data to prevent at least a portion of an unexposed region separating exposed regions from having a thickness smaller than a reference thickness by a background light that leaks from the exposed regions of the etch mask layer to the unexposed region during a photolithography process.