Three dimensional integrated circuits

• US 8,856,699 B2
• Filed: 09/10/2012
• Issued: 10/07/2014
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Yakimishu Co Ltd LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Alam, Mohammed
• Application Number:
  US13/609,108
• Publication Number:
  US 20130002296A1
• Time in Patent Office: 757 Days
• Field of Search: 716/100
• US Class Current: 716/100
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer.

Claims

1. A method comprising:

accessing a first integrated circuit design from a memory; and

converting, by using a computing device, a plurality of different circuit elements of the first integrated circuit design into a plurality of wire elements to form a second integrated circuit design, wherein the plurality of wire elements are configured to couple to at least one of a logic high source and a logic low source, wherein the first integrated circuit design is configured to perform a plurality of logic functions, and wherein the second integrated circuit design is configured to perform at least a portion of the plurality of logic functions, wherein the first integrated circuit design is programmable, and wherein the second integrated circuit design is non-programmable.

2. The method of claim 1, wherein the plurality of different circuit elements include a plurality of memory circuit elements.

3. The method of claim 1, wherein the second integrated circuit design is configured to perform at least the plurality of logic functions.

4. The method of claim 1, wherein the logic high source comprises power.

5. The method of claim 1, wherein the logic low source comprises ground.

6. A method comprising:

accessing a first integrated circuit design from a memory; and

removing, by using a computing device, a plurality of different circuit elements from the first integrated circuit design and adding, by using the computing device, a plurality of wire elements to the first integrated circuit design to form a second integrated circuit design,

wherein the plurality of wire elements are configured to couple to at least one of a logic high source and a logic low source, wherein the first integrated circuit design is configured to perform a plurality of logic functions, wherein the second integrated circuit design is configured to perform at least a portion of the plurality of logic functions, wherein the first integrated circuit design is programmable, and wherein the second integrated circuit design is non-programmable.

7. The method of claim 6, wherein the plurality of different circuit elements include a plurality of memory circuit elements.

8. The method of claim 6, wherein the second integrated circuit design is configured to perform at least the plurality of logic functions.

9. The method of claim 6, wherein the logic high source comprises power.

10. The method of claim 6, wherein the logic low source comprises ground.

11. A method comprising:

accessing a first fabrication process for an integrated circuit design from a memory; and

removing, by using a computing device, a plurality of masks from the first fabrication process and adding, by using the computing device, at least one new mask to the first fabrication process to form a second fabrication process,

wherein the at least one new mask involves a new connection to at least one of a logic high source and a logic low source, wherein the first fabrication process causes the integrated circuit design to be configured to perform a plurality of logic functions, and wherein the second fabrication process causes the integrated circuit design to be configured to perform at least a portion of the plurality of logic functions, wherein the plurality of masks involve configuring the integrated circuit design to be programmable, and wherein the at least one new mask involves configuring the integrated circuit design to be non-programmable.

12. The method of claim 11, wherein if the second fabrication process is used, the integrated circuit design is configured to perform at least the plurality of logic functions.

13. The method of claim 11, wherein the logic high source comprises power.

14. The method of claim 11, wherein the logic low source comprises ground.