Tool and method for modeling interposer RC couplings

• US 8,856,710 B2
• Filed: 06/29/2011
• Issued: 10/07/2014
• Est. Priority Date: 06/29/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Chao-Yang, Wu, Ze-Ming, Chung, Meng-Lin, Chen, Chih-Chia, Liu, Sa-Lly, Ding, Li-Fu
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): LEE, ERIC D
• Application Number:
  US13/172,248
• Publication Number:
  US 20130007692A1
• Time in Patent Office: 1,196 Days
• Field of Search: 716/115
• US Class Current: 716/115
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.

Claims

1. A method comprising:

analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium;

generating a substrate mesh model of the semiconductor interposer having a plurality of substrate mesh nodes, wherein each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements, wherein the interposer has at least one through-substrate via (TSV) extending from the front side of the interposer to the back side of the interposer, the TSV is located at one of the substrate mesh nodes, and the substrate impedance elements adjacent to the TSV have different resistance and capacitance values than other ones of the plurality of substrate impedance elements that are not adjacent to the TSV;

forming a set of inputs to a timing analysis tool, wherein the plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model; and

storing the set of inputs in a tangible machine readable storage medium.

2. The method of claim 1, further comprising:

performing a timing analysis of the semiconductor interposer using a machine implemented timing analysis tool and the set of inputs, so as to simulate frequency dependent capacitive couplings between the front side conductive patterns and backside conductive patterns.

3. The method of claim 1, wherein the nodes and the substrate impedance elements of the substrate mesh model are arranged on a three-dimensional rectangular grid having three orthogonal axes, such that each substrate impedance element is located between two adjacent ones of the nodes.

4. The method of claim 1, wherein each substrate impedance element includes a resistance and a capacitance in parallel to each other.

5. The method of claim 4, wherein each substrate impedance element further includes an inductance in parallel with the capacitance.

6. The method of claim 1, wherein

the substrate mesh model is generated to include a respective substrate mesh node adjacent to each respective RC node, and

the step of forming the set of inputs includes connecting each RC node to its respective substrate mesh node.

7. The method of claim 6, wherein the step of generating the substrate mesh model includes:

generating a respective substrate mesh node having the same in-plane coordinates as, and directly underlying, each respective RC node.

8. The method of claim 1, wherein

the substrate mesh model is generated to include a respective substrate mesh node adjacent to each respective RC node, and

the step of forming the set of inputs includes connecting each RC node to the substrate mesh node closest to that RC node, based on Euclidean distance.

9. The method of claim 8, wherein at least two of the RC nodes are connected to the same one of the substrate mesh nodes.

10. The method of claim 1, wherein the substrate mesh model has a first portion with a first node density, and a second portion with a second node density lower than the first node density.

11. The method of claim 10, wherein:

the semiconductor interposer has a first portion, in which one of the group consisting of the front side conductive patterns and the back side conductive patterns have a first density, and a second portion, in which the one of the front side conductive patterns and the back side conductive patterns have a second density lower than the first density, and

the second portion of the substrate mesh model substantially coincides with the second portion of the semiconductor interposer.

12. The method of claim 11, wherein the nodes of the substrate mesh model are arranged on a rectangular grid, and the step of generating a substrate mesh model includes:

generating a preliminary model having a uniform node density; and

deleting from the preliminary model a first node of the substrate mesh, such that all of the plurality of RC nodes is more than a threshold distance from the location of the first node.

13. The method of claim 11, wherein the nodes of the substrate mesh model are arranged on a rectangular grid, and the step of generating a substrate mesh model includes:

generating a preliminary model having a uniform node density; and

deleting from the preliminary model a first node, such that four rectangles defined by the first node and additional nodes adjacent to the first node do not underlie any front side conductive pattern of the semiconductor interposer.

14. The method of claim 1, further comprising

performing a timing analysis of the semiconductor interposer using a machine implemented timing analysis tool and the set of inputs, so as to simulate frequency dependent capacitive couplings between the front side conductive patterns and backside conductive patterns;

and

fabricating the semiconductor interposer if the timing analysis indicates that a design of the semiconductor interposer satisfies a predetermined timing specification; and

incorporating the semiconductor interposer into a 2.5D package.

15. A system comprising:

a processor-implemented RC extraction tool for analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer, and outputting data representing a plurality of respective RC nodes;

a processor-implemented substrate extraction tool for generating a substrate mesh model of the semiconductor interposer having a plurality of substrate mesh nodes, wherein each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements, wherein the interposer has at least one through-substrate via (TSV) extending from the front side of the interposer to the back side of the interposer, the TSV is located at one of the substrate mesh nodes, and the substrate impedance elements adjacent to the TSV have different resistance and capacitance values than other ones of the plurality of substrate impedance elements that are not adjacent to the TSV; and

a tangible persistent machine readable storage medium for storing a set of inputs to a timing analysis tool, wherein the plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model.

16. The system of claim 15, further comprising:

a machine implemented timing analysis tool for performing a timing analysis of the semiconductor interposer using the set of inputs, so as to simulate frequency dependent capacitive couplings between the front side conductive patterns and backside conductive patterns.

17. The system of claim 16, wherein:

the nodes and the substrate impedance elements of the substrate mesh model are arranged on a three-dimensional rectangular grid having three orthogonal axes, such that each substrate impedance element is located between two adjacent ones of the nodes, each substrate impedance element including a resistance and a capacitance in parallel to each other;

the substrate mesh model is generated to include a respective substrate mesh node adjacent to each respective RC node,

the step of forming the set of inputs includes connecting each RC node to its respective substrate mesh node; and

the step of generating the substrate mesh model includes generating a respective substrate mesh node having the same in-plane coordinates as, and directly underlying, each respective RC node.

18. A tangible persistent machine readable storage medium having machine readable program instructions encoded therein, such that when the program instructions are executed by a processor, the processor performs a method comprising:

analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool;

generating a substrate mesh model of the semiconductor interposer having a plurality of substrate mesh nodes, wherein each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements, wherein the interposer has at least one through-substrate via (TSV) extending from the front side of the interposer to the back side of the interposer, the TSV is located at one of the substrate mesh nodes, and the substrate impedance elements adjacent to the TSV have different resistance and capacitance values than other ones of the plurality of substrate impedance elements that are not adjacent to the TSV;

forming a set of inputs to a timing analysis tool, wherein the plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model; and

storing the set of inputs in a tangible machine readable storage medium.

19. The storage medium of claim 18, wherein the method further comprises:

performing a timing analysis of the semiconductor interposer using a machine implemented timing analysis tool and the set of inputs, so as to simulate frequency dependent capacitive couplings between the front side conductive patterns and backside conductive patterns.

20. The storage medium of claim 18, wherein the nodes and the substrate impedance elements of the substrate mesh model are arranged on a three-dimensional rectangular grid having three orthogonal axes, such that each substrate impedance element is located between two adjacent ones of the nodes.