High speed communication jack

• US 8,858,266 B2
• Filed: 01/11/2013
• Issued: 10/14/2014
• Est. Priority Date: 02/13/2012
• Status: Active Grant

• Current Assignee: Sentinel Connector Systems, Inc.
• Original Assignee: Sentinel Connector Systems, Inc.
• Inventors: Robinson, Brett D.
• Primary Examiner(s): GUSHI, ROSS N
• Application Number:
  US13/739,214
• Publication Number:
  US 20130210277A1
• Time in Patent Office: 641 Days
• Field of Search: 439/676, 439/607.38, 43962017-62019, 439/620.11, 439/620.23
• US Class Current: 439/676
• CPC Class Codes: H01R 13/646 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match non-coaxed protective earth or shield arrangements H01R13/648; coaxed connectors specially adapted for high frequency H01R24/40
• CPC Class Codes: H01R 13/6474 by variation of conductive properties, e.g. by dimension variations
• CPC Class Codes: H01R 13/6581 Shield structure
• CPC Class Codes: H01R 13/6625 with capacitive component
• CPC Class Codes: H01R 13/6658 on printed circuit board H01R13/6666 - H01R13/6691 take precedence
• CPC Class Codes: H01R 13/7195 with planar filters with openings for contacts
• CPC Class Codes: H01R 2107/00 Four or more poles
• CPC Class Codes: H01R 24/64 for high frequency, e.g. RJ 45
• CPC Class Codes: H01R 43/205 with a panel or printed circuit board
• CPC Class Codes: H05K 1/0218 by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 1/0228 Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors balanced signal pairs H05K1/0245
• CPC Class Codes: H05K 1/09 Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49218 with deforming

Abstract

A high speed communication jack including a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug and a shielding case surrounding the housing. A flexible circuit board between the shielding case and the housing having a substrate, a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing, a plurality of traces on a first side of the substrate, with each trace extending from a corresponding one of the plurality of vias, and a shielding plane on a second side of the substrate opposite the first side of the substrate.

Claims

1. A high speed communication jack including:

a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug;

a shielding case surrounding the housing;

a flexible circuit board between the shielding case and the housing having

a substrate,

a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing,

a plurality of traces on a first side of the substrate, with each trace extending from a corresponding one of the plurality of vias, and

a shielding plane on a second side of the substrate opposite the first side of the substrate.

2. The jack of claim 1 wherein, when energized, each trace of the plurality of traces is differentially matched to a second adjacent trace of the plurality of traces.

3. The jack of claim 2 wherein the impedance value of a first trace in a matched pair of traces is adjusted to be substantially equal to the impedance value of the second trace in the matched pair of traces.

4. The jack of claim 3 wherein the width, height or length of each trace in matched set of traces is adjusted such that the impedance of the first trace matches the impedance of the second trace.

5. The jack of claim 3 wherein the impedance of the first trace and second trace are adjusted such that the traces are matched when a first signal is transmitted on the first trace and a second signal is transmitted on the second trace.

6. The jack of claim 1 wherein a capacitor is formed in each via by a trace layer and a return signal layer embedded in a dielectric layer.

7. The jack of claim 6 wherein a distance between the return signal layer and the trace layer is adjusted such that the capacitor has a value of between approximately 1 pf and approximately 5 pf.

8. The jack of claim 6 wherein a second return signal layer is formed in the dielectric layer below the first return signal layer to form a second capacitor.

9. The jack of claim 8 wherein the distance between the first signal layer and second signal layer is adjusted to adjust the value of the second capacitor between 1 pf and 5 pf.

10. The jack of claim 6 wherein the capacitor, trace and return signal layer form a common mode filter with the matched set of traces.

11. The jack of claim 10 wherein the value of the capacitor is adjusted such that the common mode filter prevents reflections of signals from the matched traces.

12. The jack of claim 11 including a second shielding tab on a side of the substrate opposite the first shielding.

13. The jack of claim 1 wherein the traces are plated in gold.

14. The jack of claim 1, wherein the substrate includes a dielectric material having a dielectric constant greater than 3.0.

15. A high speed communication jack comprising a standard RJ45 housing having a port for accepting a plug, the port including a plurality of pins connected to a corresponding signal line in the plug, the jack comprising:

a shielding case surrounding the housing

a flexible circuit board between the shielding case and the housing having

a substrate,

a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing,

a plurality of traces on a first side of the substrate, with each trace extending from a corresponding one of the plurality of vias, and

a shielding plane on a second side of the substrate opposite the first side of the substrate.

16. A method of manufacturing a high speed communication jack using a standard RJ45 housing having a front surface, back surface, top surface, bottom surface, right surface and left surface, the housing including a plurality of pins each connected to a corresponding signal line in the plug, the method including the steps of:

forming a flexible circuit board having a substrate, a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing, a plurality of traces on a first side of the substrate, with each trace extending from a corresponding one of the plurality of vias, a shielding plane on a second side of the substrate opposite the first side of the substrate, and at least two shielding tabs on opposite ends of the flexible circuit board and connected to the electrical circuit board by a shielding trace,

inserting each via in the flexible circuit board into a corresponding pin in the housing;

bending the flexible circuit board such that a portion of the flexible circuit board having the vias is on the bottom surface of the housing and is orthogonal to the portion of the flexible circuit board having the shielding plane that is on the back portion of the housing;

bending each shielding tab such that they one shielding tab is in contact with the left side surface and one shielding tab is in contact with the right side surface of the housing; and

forming a shielding case over the flexible circuit board and the housing such that the shielding case is in contact with each of the shielding tabs.

17. A high speed communication jack including:

a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug;

a shielding case surrounding the housing

a multilayer flexible circuit board between the shielding case and the housing having

a first layer having a plurality of traces,

a second layer of a dielectric material on a side of the first layer opposite the traces,

a third layer on a side of the second layer opposite the first layer and having a return plane made from a conductive material;

a fourth layer on a side of the third layer opposite the second layer and made of a dielectric material;

a fifth layer on a side of the fourth layer opposite the third layer and made of a conductive material;

a plurality of vias extending through the first, second, third, fourth and fifth layers, with each via being configured to accommodate a pin on the housing.

18. The jack of claim 17 wherein a capacitor is formed in each via by the combination of one of the plurality of traces on the first layer, the second layer and the third layer.

19. The jack of claim 18 wherein the depth of the second layer is adjusted such that the capacitor in each via has a value of between approximately 1 pf and approximately 5 pf.

20. The jack of claim 17 including

a sixth layer formed between the fourth layer and fifth layer, with the sixth layer being made of a conductive material, and

a seventh layer formed between the sixth layer and the fifth layer, with the seventh layer being made of a dielectric material.