Apparatus and methods for deposition and/or etch selectivity

• US 8,858,763 B1
• Filed: 02/24/2009
• Issued: 10/14/2014
• Est. Priority Date: 11/10/2006
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Klawuhn, Erich R., Rozbicki, Robert, Dixit, Girish A.
• Primary Examiner(s): MCDONALD, RODNEY GLENN
• Application Number:
  US12/391,719
• Time in Patent Office: 2,058 Days
• Field of Search: 204/192.17, 438/582, 438/656, 438/685, 438/686, 438/687
• US Class Current: 204/192.17
• CPC Class Codes: C23C 14/046 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 14/3407 Cathode assembly for sputtering apparatus, e.g. Target
• CPC Class Codes: C23C 14/345 using substrate bias
• CPC Class Codes: C23C 14/3492 Variation of parameters during sputtering
• CPC Class Codes: C23C 14/35 by application of a magnetic field, e.g. magnetron sputtering C23C14/3457 takes precedence
• CPC Class Codes: H01J 37/32596 Hollow cathodes
• CPC Class Codes: H01J 37/3405 Magnetron sputtering
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/32131 by physical means only
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76868 Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films

Abstract

Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.

Claims

1. A method for depositing material on a semiconductor wafer having recessed features of different depths, including a plurality of vias traversing a layer of the semiconductor wafer and a plurality of trenches extending into but not traversing the layer of the semiconductor wafer, the method comprising:

depositing a first coverage amount of material in each via to coat a bottom of each said via; and

simultaneously with depositing the first coverage amount of material, depositing a second coverage amount of material in each trench to coat a bottom of each said trench

wherein the depositing of the first and second coverage amounts are selectively controlled such that a ratio of the second coverage amount over the first coverage amount is greater than about 1.2.

2. A method as recited in claim 1, wherein the ratio is greater than about 2.5.

3. A method as recited in claim 1, wherein the first coverage amount of material is deposited in substantially only in a direction that is substantially normal to a surface of the wafer and the second coverage amount of material is deposited in a plurality of directions in relation to the wafer surface, including a normal direction and a substantially non-normal angle.

4. A method as recited in claim 3, wherein the deposition of the first and second coverage amounts is performed by an apparatus having (a) a process chamber having a target for depositing material onto the semiconductor wafer, and (b) a wafer support for holding the wafer in position during deposition of the material, the method further comprising positioning the wafer with respect to the target so that the second coverage amount of material deposited in each trench is greater than the first coverage amount of material deposited in each via, and wherein the deposition is performed by sputtering material from the target onto the semiconductor wafer.

5. A method as recited in claim 4, wherein the target is three dimensional and has a top target surface and a sidewall target surface and wherein the material that is sputtered from the sidewall target surface is used to cover the bottom surfaces of the trenches in a greater amount than the bottom surfaces of the vias.

6. A method as recited in claim 5, wherein the material is deposited by generating a magnetic field on the sidewall target surface so that a separatrix is formed.

7. A method as recited in claim 6 wherein the separatrix is formed at a bottom edge of the sidewall target surface that is the closest edge to the wafer and wherein the wafer is positioned greater than 0 and less than about 10 centimeters from the bottom edge.

8. A method as recited in claim 6, wherein the separatrix is formed in a top half of the sidewall target surface that is positioned farthest from the wafer and the wafer is positioned adjacent to at least a portion of the sidewall target surface.

9. A method as recited in claim 8, wherein the wafer is positioned between about −

1 and +10 centimeters from a bottom edge of the sidewall target surface that is closest to the wafer.

10. A method as recited in claim 4, wherein the target is three dimensional and formed from at least a first target piece and a second target piece, wherein the first target piece has a surface that is parallel with the wafer surface on which the recessed features are formed and the second target piece has a surface that is substantially perpendicular to the wafer surface on which the recessed features are formed.

11. A method as recited in claim 10, wherein the deposition is accomplished by generating a magnetic field on the second target piece of the target so that a separatrix is formed.

12. A method as recited in claim 11, wherein the separatrix is formed at a bottom edge of the second target piece of the target that is the closest edge to the wafer and wherein the wafer is positioned greater than 0 and less than about 10 centimeters from the bottom edge.

13. A method as recited in claim 11, wherein the separatrix is formed in a top half of the second target piece that is positioned farthest from the wafer and the wafer is positioned adjacent to at least a portion of the second target piece.

14. A method as recited in claim 13, wherein the wafer is positioned between about −

1 and +10 centimeters from a bottom edge of the second target piece that is closest to the wafer.

15. A method of claim 4, wherein the deposition of the first and second coverage amounts performed by sputtering material from the target includes generating a plasma comprising ionized material sputtered from the target.

16. A method of claim 15, wherein the target comprises a metal for forming a diffusion barrier on the semiconductor wafer.

17. A method of claim 16, wherein the diffusion barrier comprises at least one of the following:

Ta, TaN_X, Ti, TiN_X, W, WN_X, Ru, or Co.

18. A method as recited in claim 16, further comprising resputtering substantially all of the first coverage amount of material from each via without damaging a dielectric material that lies beneath each trench.

19. The method of claim 1, further comprising:

after depositing the first coverage amount of material in each via and depositing the second coverage amount of material in each trench, etching the material deposited in each said via and each said trench such that the material deposited in each said via is removed enough to expose at least a portion of the layer of the wafer underneath each said via, while an amount of the material deposited in each said trench remains on the bottom surface of each said trench.

20. The method of claim 19, wherein the ratio is greater than about 2.5.