Semiconductor device and fabrication method thereof

• US 8,859,353 B2
• Filed: 09/09/2013
• Issued: 10/14/2014
• Est. Priority Date: 07/06/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Arai, Yasuyuki, Koyama, Jun
• Primary Examiner(s): Diaz, Jose R
• Application Number:
  US14/021,168
• Publication Number:
  US 20140011331A1
• Time in Patent Office: 400 Days
• Field of Search: 257/59, 257/72, 438/430, 438151-166, 349/155
• US Class Current: 438/164
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/13396 Spacers having different sizes
• CPC Class Codes: G02F 1/13398 Spacer materials; Spacer properties
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02208 the precursor containing a compound comprising Si
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02532 : Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 : amorphous
• CPC Class Codes: H01L 21/0262 : Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 : Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02667 : Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/0273 : characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/3065 : Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 : characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 27/12 : the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 : with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1248 : with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 : comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1274 : using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 27/1288 : employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/167 : further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66757 : Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/7833 : with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/78621 : with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78672 : Polycrystalline or microcrystalline silicon transistor
• CPC Class Codes: H01L 29/78675 : with normal-type structure, e.g. with top gate
• CPC Class Codes: Y10S 438/919 : Compensation doping

Abstract

A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an inter-layer insulation film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Claims

1. A method of fabricating a semiconductor device having, on the same substrate, a pixel TFT disposed in a pixel unit and a driving circuit including a p channel type TFT and an n channel type TFT and disposed round the pixel unit, comprising the steps of:

forming an underlying film over the substrate;

forming island-like semiconductor layers over the underlying film;

forming n type impurity regions having a first concentration, for forming LDD regions of the n channel type TFT and the pixel TFT in a selected region of the island-like semiconductor layers;

forming high concentration n type impurity regions for forming source regions or drain regions outside the n type impurity regions;

forming a p type impurity region having a third concentration, for forming a source region or a drain region of the p channel type TFT in a selected region of the island-like semiconductor layers;

forming a protective insulation film formed of an inorganic insulating material above gate electrodes of the n channel type TFT, the pixel TFT and the p channel type TFT;

foaming an inter-layer insulation film formed of an organic insulating material in contact with the protective insulation film;

forming a conductive metal lead wire to be electrically connected to the pixel TFT; and

forming a pixel electrode comprising a transparent conductor film to be electrically connected to the conductive metal lead wire, on the inter-layer insulation film,

wherein the step of forming the p type impurity region having the third concentration is conducted after the step of forming the protective insulation film so that an offset region is formed between a channel formation region of the p channel type TFT and the p type impurity region having the third concentration.

2. A method according to claim 1, further comprising the step of:

forming a gate lead wire extending from the driving circuit and to be electrically connected to the gate electrodes, from a low resistance conductive material,

wherein the gate electrodes are formed a heat-resistant conductive material.

3. A method according to claim 2, wherein the heat-resistant conductive material is an element selected from tantalum, titanium, molybdenum and tungsten, or a compound consisting of the element as a principal component, or a compound comprising the combination of the elements, or a nitride containing the element as a component or a silicide containing the element as a component.

4. A method according to claim 1, wherein the semiconductor device is one member selected from the group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disk player, an electronic game machine and a projector.

5. A method of fabricating a semiconductor device having a liquid crystal sandwiched between a pair of substrates, comprising, the following steps for one of substrates including a pixel TFT disposed in a pixel unit and a driving circuit having a p channel type TFT and an n channel type TFT round the pixel unit:

forming an underlying film over the one of substrates;

forming island-like semiconductor layers over the underlying film;

forming n type impurity regions having a first concentration, for forming LDD regions of the n channel type TFT and the pixel TFT, in a selected region of the island-like semiconductor layers;

forming n type impurity regions having a second concentration, for forming source regions or drain regions outside the n type impurity regions having the first concentration;

forming a p type impurity region having a third concentration, for forming a source region or a drain region of the p channel type TFT, in a selected region of the island-like semiconductor layers;

forming a protective insulation film formed of an inorganic insulating material above gate electrodes of the n channel type TFT, the pixel TFT and the p channel type TFT;

forming an inter-layer insulation film formed of an organic insulating material in contact with the protective insulation film;

forming on the inter-layer insulation film a pixel electrode electrically connected to the pixel TFT through a hole in the inter-layer insulation film and in the protective insulation film;

forming at least a transparent conductor film over the other of the substrates; and

bonding the one of substrates to the other of the substrates through at least one columnar spacer formed in superposition with the hole,

wherein the step of forming the p type impurity region having the third concentration is conducted after the step of forming the protective insulation film so that an offset region is formed between a channel formation region of the p channel type TFT and the p type impurity region having the third concentration.

6. A method according to claim 5, further comprising the step of:

forming a gate lead wire extending from the driving circuit and to be electrically connected to the gate electrodes, from a low resistance conductive material,

wherein the gate electrodes are formed a heat-resistant conductive material.

7. A method according to claim 6, wherein the heat-resistant conductive material is an element selected from tantalum, titanium, molybdenum and tungsten, or a compound consisting of the element as a principal component, or a compound comprising the combination of the elements, or a nitride containing the element as a component or a silicide containing the element as a component.

8. A method according to claim 5, wherein the semiconductor device is one member selected from the group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disk player, an electronic game machine and a projector.

9. A method according to claim 5, wherein the columnar spacer is formed also over the p channel type TFT and the n channel type TFT.

10. A method according to claim 5, wherein the columnar spacer is formed in such a fashion as to cover at least a source lead wire or a drain lead wire of the p channel type TFT and the n channel type TFT.

11. A method according to claim 5, further comprising the step of:

forming a conductive metal lead wire electrically connected to the pixel TFT a hole bored in the inter-layer insulation film and the protective insulation film before the formation of the pixel electrode,

wherein the pixel electrode includes a transparent conductor film and is electrically connected to the conductive metal lead wire;

12. A method according to claim 5, wherein the pixel electrode has a light reflecting surface.

13. A method of fabricating a semiconductor device having, on the same substrate, a pixel TFT disposed in a pixel unit and a driving circuit including an n channel type TFT and disposed round the pixel unit, the method comprising:

forming at least two island-like semiconductor layers over the substrate;

forming a gate electrode over each of the at least two island-like semiconductor layers;

introducing a first n type impurity into each of the at least two island-like semiconductor layers at a first concentration by using the gate electrode as a mask;

introducing a second n type impurity into each of the at least two island-like semiconductor layers at a second concentration by using the gate electrode as a mask and by using a resist as a mask to form an LDD region having the first concentration in the pixel TFT and the n channel type TFT and to form a source region and a drain region having the second concentration in the pixel TFT and the n channel type TFT;

forming a protective insulation film formed of an inorganic insulating material over the gate electrode;

activating the first n type impurity and the second n type impurity after the formation of the protective insulation film; and

forming an inter-layer insulation film formed of an organic insulating material over the protective insulation film after the activation.

14. A method according to claim 13, wherein the activation is conducted by a thermal annealing method, a laser annealing method, or a rapid thermal annealing method.

15. A method according to claim 13, wherein the first n type impurity is same as the second n type impurity.

16. A method according to claim 13, wherein the gate electrode comprises an element selected from the group consisting of tantalum, titanium, molybdenum and tungsten, or a compound consisting of the element as a principal component, or a compound comprising the combination of the elements, or a nitride containing the element as a component or a silicide containing the element as a component.

17. A method according to claim 13, wherein the semiconductor device is one member selected from the group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disk player, an electronic game machine and a projector.

18. A method according to claim 15,

wherein each of the gate electrodes includes a first conductor layer and a second conductor layer over the first conductor layer, and

wherein an oxygen concentration in the second conductor layer is 30 ppm or below.