Methods of fabricating silicon carbide devices having smooth channels

• US 8,859,366 B2
• Filed: 05/14/2012
• Issued: 10/14/2014
• Est. Priority Date: 05/24/2005
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Das, Mrinal K., Laughner, Michael
• Primary Examiner(s): Pham, Long
• Application Number:
  US13/470,600
• Publication Number:
  US 20120228638A1
• Time in Patent Office: 883 Days
• Field of Search: 438/268, 438/285, 438/692, 438/931
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

Methods of forming silicon carbide power devices are provided. An n⁻ silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n⁻ silicon carbide layer. A buried region of p⁺ silicon carbide is provided on the p-type silicon carbide well region. An n⁺ region of silicon carbide is provided on the buried region of p⁺ silicon carbide. A channel region of the power device is adjacent the buried region of p⁺ silicon carbide and the n⁺ region of silicon carbide. An n⁻ region is provided on the channel region and a portion of the n⁻ region is removed from the channel region so that a portion of the n⁻ region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Claims

1. A method of forming a silicon carbide power device, comprising:

providing an n-type silicon carbide region;

providing a p-type silicon carbide region adjacent the n-type silicon carbide region; and

providing an n⁻

silicon carbide region only on a channel region of the device that provides a reduction in surface roughness of the channel region of the silicon carbide power device;

wherein the channel region of the silicon carbide power device includes at least portions of the n-type silicon carbide region, the p-type silicon carbide region and the n⁻

silicon carbide region.

2. The method of claim 1:

wherein the n-type silicon carbide region and p-type silicon carbide region include steps of up to several hundred angstroms in height on surfaces thereof; and

wherein the n⁻

silicon carbide region is provided on the steps on the surfaces of the n-type silicon carbide region and p-type silicon carbide region in the channel region, the presence of the n⁻

silicon carbide region on the steps providing the reduction in surface roughness of the channel region of the silicon carbide power device.

3. The method of claim 2, wherein the reduction in the surface roughness is a reduction in a root mean square (RMS) surface roughness of from at least about 28 Å

to less than about 1.0 Å

.

4. The method of claim 2, wherein the channel region of the silicon carbide power device has a root mean square (RMS) surface roughness of less than about 1.0 Å

.

5. The method of claim 2, further comprising providing a gate insulating layer on the n-type silicon carbide layer and the p-type silicon carbide region, wherein the n⁻

silicon carbide region fills in peaks and valleys on the surfaces of the n-type silicon carbide layer and the p-type silicon carbide region to provide a smoother interface between the channel region and a gate insulating layer.

6. The method of claim 2, wherein providing an n⁻

region comprises;

forming an n-type epitaxial layer on the n-type silicon carbide region and the p-type silicon carbide region; and

selectively removing a portion of the n-type epitaxial layer to provide the n⁻

region so that a portion of the n⁻

region remains on the steps to provide the reduction in a surface roughness of the channel region.

7. The method of claim 6, wherein selectively removing comprises performing a chemical mechanical polishing (CMP) process on the n-type epitaxial layer that removes only a portion of the n⁻

region from the channel region.

8. The method of claim 7, wherein the CMP process is performed for less than about 3.0 hours.

9. The method of claim 8, wherein the CMP process is performed for from about half an hour to about one hour.

10. The method of claim 7, wherein the CMP process removes all but from about 1000 to about 5000 Å

of the n-type epitaxial layer from the channel region.

11. The method of claim 7, wherein selectively removing further comprises removing a portion of the n-type epitaxial layer that is from about 2.0 to about 3.0 times a depth of the surface roughness of the channel region.

12. The method of claim 2, further comprising providing a sacrificial oxide layer on the channel region and removing the same, wherein the providing and removing of the sacrificial oxide layer further reduces the RMS surface roughness of the channel region.

13. The method of claim 12, wherein the RMS surface roughness of the surface of the channel region is no greater than about 0.7 Å

.

14. The method of claim 2, where providing the n⁻

silicon carbide region comprises providing an n⁻

silicon carbide region having a thickness from about 1000 to about 5000 Å

.

15. A method of forming a silicon carbide power device, comprising:

providing an n-type silicon carbide region;

providing a p-type silicon carbide region adjacent the n-type silicon carbide region; and

providing an n⁻

silicon carbide region that provides a reduction in surface roughness of a channel region of the silicon carbide power device;

wherein the channel region of the silicon carbide power device includes at least portions of the n-type silicon carbide region, the p-type silicon carbide region and the n⁻

silicon carbide region;

wherein the n-type silicon carbide region and p-type silicon carbide region include steps of up to several hundred angstroms in height on surfaces thereof; and

wherein the n⁻

silicon carbide region is provided on the steps on the surfaces of the n-type silicon carbide region and p-type silicon carbide region, the presence of the n⁻

silicon carbide region on the steps providing the reduction in surface roughness of the channel region of the silicon carbide power device.