Semiconductor device

• US 8,860,039 B2
• Filed: 04/07/2011
• Issued: 10/14/2014
• Est. Priority Date: 04/26/2010
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Miura, Naruhisa, Nakata, Shuhei, Ohtsuka, Kenichi, Watanabe, Shoyu, Watanabe, Hiroshi
• Primary Examiner(s): Green, Telly
• Assistant Examiner(s): Hillman, Damian A
• Application Number:
  US13/638,970
• Publication Number:
  US 20130020586A1
• Time in Patent Office: 1,286 Days
• Field of Search: 257/77, 257/107, 257/2
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a drift layer of the first conductivity type formed on a surface of said semiconductor substrate;

a plurality of first well regions of a second conductivity type formed selectively in a surface region of said drift layer;

a source region of the first conductivity type formed selectively in a surface region of each of said first well regions;

a gate electrode formed over said first well regions and said drift layer thereacross through an insulating film;

a second well region of the second conductivity type in said drift layer below said gate electrode, and connected to each of said first well regions adjacent to one another;

a source electrode connected to said source region; and

a drain electrode formed on a rear surface of said semiconductor substrate,

wherein a second conductivity type impurity concentration profile of said second well region in a depth direction includes a point which is deeper than said surface region of said drift layer and where a second conductivity type impurity concentration at said point is higher than a second conductivity type impurity concentration at said surface region of said drift layer.

2. The semiconductor device according to claim 1,

wherein said second well region is connected among a plurality of adjacent ones of said first well regions.

3. The semiconductor device according to claim 2,

wherein said second well region is formed to include a position in plan view at which a total sum of distances between said second well region and said plurality of first well regions to which said second well region is connected becomes a minimum.

4. The semiconductor device according to claim 1, further comprising a peripheral region of the second conductivity type formed selectively in the surface region of said drift layer in a manner to surround, in a plan view, a cell region including said plurality of first well regions, and connected to said source electrode.

5. The semiconductor device according to claim 1,

wherein said first well regions and said second well region are different from each other in a distribution of an impurity concentration of the second conductivity type.

6. The semiconductor device according to claim 1,

wherein the semiconductor device comprises a plurality of said second well regions, and

the semiconductor device further comprises third well regions of the second conductivity type formed to be buried inside said drift layer among said plurality of first well regions and formed to be individually connected to each of said second well regions adjacent to one another.

7. The semiconductor device according to claim 6,

wherein an upper surface of said third well region is formed below a lower surface of said first well region.

8. The semiconductor device according to claim 6,

wherein said second well region and said third well region are formed to cover all regions among said plurality of first well regions in plan view.

9. The semiconductor device according to claim 6, further comprising a first impurity region of the first conductivity type formed below said second well region and/or said third well region, and having an impurity concentration higher than an impurity concentration of said drift layer.

10. The semiconductor device according to claim 1, further comprising a second impurity region of the first conductivity type provided in the surface region of said drift layer below said gate electrode and having an impurity concentration higher than an impurity concentration of said drift layer.

11. The semiconductor device according to claim 1,

wherein gaps between said first well regions and said source region are identical throughout on the surface region of said drift layer.

12. The semiconductor device according to claim 11,

wherein said first well region is circular.

13. The semiconductor device according to claim 1,

wherein said semiconductor substrate is formed of a wide bandgap semiconductor.

14. The semiconductor device according to claim 13,

wherein said wide bandgap semiconductor is a silicon carbide.

15. The semiconductor device according to claim 1, wherein a depth of said first well regions is substantially the same as a depth of said second well region.

16. The semiconductor device according to claim 1, wherein said second well region has a triangular shape in plan view.

17. The semiconductor device according to claim 1, wherein said second well region of the second conductivity type is completely buried within said drift layer.

18. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a drift layer of the first conductivity type formed on a surface of said semiconductor substrate;

a plurality of first well regions of a second conductivity type formed selectively in a surface region of said drift layer;

a source region of the first conductivity type formed selectively in a surface region of each of said first well regions;

a JFET region which is in a gap region between said first well regions adjacent to one another;

a gate electrode formed over said first well regions and said JFET region thereacross through an insulating film;

a second well region of the second conductivity type in said JFET region, and connected to each of said first well regions adjacent to one another;

a layer formed between said insulating film and said second well region, and in which a second conductivity type impurity concentration is lower than a second conductivity type impurity concentration in said second well region;

a source electrode connected to said source region; and

a drain electrode formed on a rear surface of said semiconductor substrate.

19. The semiconductor device according to claim 18, wherein said second well region of the second conductivity type is completely buried within said JFET region.