Oxide-based thin-film transistor (TFT) semiconductor memory device having source/drain electrode of one transistor connected to gate electrode of the other

• US 8,860,108 B2
• Filed: 10/26/2010
• Issued: 10/14/2014
• Est. Priority Date: 10/30/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): MAI, ANH D
• Application Number:
  US12/912,190
• Publication Number:
  US 20110101334A1
• Time in Patent Office: 1,449 Days
• Field of Search: 257/43, 257/296, 257/300, 257/368, 257/E27.084
• US Class Current: 257/296
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

Claims

1. A semiconductor device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a fifth wiring,

wherein a plurality of memory elements are supported by a substrate including a semiconductor material, and connected in series between the first wiring and the second wiring, each memory element comprising;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,

wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,

wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the fourth wiring and the second gate electrode are electrically connected to each other, and

wherein the fifth wiring and the third gate electrode are electrically connected to each other.

2. A semiconductor device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a fifth wiring,

wherein a plurality of memory elements are supported by a substrate including a semiconductor material, and connected in series between the first wiring and the second wiring, each memory element comprising;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,

wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,

wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the fourth wiring and the second gate electrode are electrically connected to each other, and

wherein the fifth wiring and the third gate electrode are electrically connected to each other.

3. The semiconductor device according to claim 2 further comprising:

a sixth wiring;

a seventh wiring;

a fourth transistor with a gate electrode electrically connected to the sixth wiring; and

a fifth transistor with a gate electrode electrically connected to the seventh wiring,

wherein the second wiring is electrically connected to the first drain electrode and the third drain electrode through the fourth transistor, and

wherein the first wiring is electrically connected to the first source electrode and the third source electrode through the fifth transistor.

4. The semiconductor device according to claim 2, wherein the second transistor comprises the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

5. The semiconductor device according to claim 2, wherein the first transistor comprises a channel formation region provided in the substrate including the semiconductor material, at least a first impurity region and a second impurity region between which is provided the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode being located over the first gate insulating layer, and the first source electrode being electrically connected to one of the first impurity region and the second impurity region, and the first drain electrode being electrically connected to the other one of the first impurity region and the second impurity region.

6. The semiconductor device according to claim 2 wherein the third transistor comprises a channel formation region provided in the substrate including the semiconductor material, at least a first impurity region and a second impurity region between which is provided the channel formation region, a third gate insulating layer over the channel formation region, the third gate electrode being located over the third gate insulating layer, the third source electrode being electrically connected to one of the first impurity region and the second impurity region, and the third drain electrode being electrically connected to the other one of the first impurity region and the second impurity region.

7. The semiconductor device according to claim 2, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

8. The semiconductor device according to claim 2, wherein the semiconductor material is silicon.

9. The semiconductor device according to claim 2, wherein the oxide semiconductor layer includes an In—

Ga—

Zn—

O-based oxide semiconductor material.

10. The semiconductor device according to claim 2, wherein the oxide semiconductor layer includes a crystal of In₂Ga₂ZnO₇.

11. The semiconductor device according to claim 2, wherein a concentration of hydrogen of the oxide semiconductor layer is 5×

10¹⁹ atoms/cm³ or less.

12. The semiconductor device according to claim 2, wherein an off-state current of the second transistor is 1×

10<sup>−

13</sup> A or less.

13. A semiconductor device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a fifth wiring;

a substrate comprising a semiconductor material;

a first insulating layer over the substrate;

a second insulating layer over the first insulating layer;

embedded conductive layers embedded in the second insulating layer, the embedded conductive layers and the second insulating layer having a same thickness, and bottom surfaces of the embedded conductive layers coinciding with a bottom surface of the second insulating layer;

a third insulating layer over the second insulating layer and the embedded conductive layers;

wherein a plurality of memory elements are supported by the substrate, and connected in series between the first wiring and the second wiring, each memory element comprising;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising, a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,

wherein the second transistor includes an oxide semiconductor layer,

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,

wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,

wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the fourth wiring and the second gate electrode are electrically connected to each other,

wherein the fifth wiring and the third gate electrode are electrically connected to each other,

wherein the first insulating layer is formed over the gate electrode of the first transistor;

wherein the second gate electrode is formed by one of the embedded conductive layers; and

wherein the third insulating layer forms a gate insulating layer of the second electrode.

14. The semiconductor device according to claim 13 further comprising:

a sixth wiring;

a seventh wiring;

a fourth transistor with a gate electrode electrically connected to the sixth wiring; and

a fifth transistor with a gate electrode electrically connected to the seventh wiring,

wherein the second wiring is electrically connected to the first drain electrode and the third drain electrode through the fourth transistor, and

wherein the first wiring is electrically connected to the first source electrode and the third source electrode through the fifth transistor.

15. A semiconductor device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a fifth wiring;

a substrate comprising a semiconductor material;

a first insulating layer over the substrate;

a second insulating layer over the first insulating layer;

embedded conductive layers embedded in the second insulating layer, the embedded conductive layers and the second insulating layer having a same thickness, and bottom surfaces of the embedded conductive layers coinciding with a bottom surface of the second insulating layer;

a third insulating layer over the second insulating layer and the embedded conductive layers;

wherein a plurality of memory elements are supported by the substrate, and connected in series between the first wiring and the second wiring, each memory element comprising;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising, a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,

wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,

wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the fourth wiring and the second gate electrode are electrically connected to each other,

wherein the fifth wiring and the third gate electrode are electrically connected to each other,

wherein the first insulating layer is formed over the gate electrode of the first transistor;

wherein the second gate electrode is formed by one of the embedded conductive layers; and

wherein the third insulating layer forms a gate insulating layer of the second electrode.

16. The semiconductor device according to claim 15 further comprising:

a sixth wiring;

a seventh wiring;

a fourth transistor with a gate electrode electrically connected to the sixth wiring; and

a fifth transistor with a gate electrode electrically connected to the seventh wiring,

wherein the second wiring is electrically connected to the first drain electrode and the third drain electrode through the fourth transistor, and

wherein the first wiring is electrically connected to the first source electrode and the third source electrode through the fifth transistor.