Semiconductor structure having aluminum layer with high reflectivity

• US 8,860,135 B2
• Filed: 02/21/2012
• Issued: 10/14/2014
• Est. Priority Date: 02/21/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsu, Chi-Mao, Huang, Hsin-Fu, Tsai, Min-Chuan, Chen, Chien-Hao, Chen, Wei-Yu, Lin, Chin-Fu, Li, Jing-Gang, Chen, Min-Hsien, Su, Jian-Hong
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US13/401,788
• Publication Number:
  US 20130214336A1
• Time in Patent Office: 966 Days
• Field of Search: 257/758, 257/765, 257/771, 257/E21.577, 257/E21.585, 257/330, 257/334, 257/335, 257/337, 257/E29.261
• US Class Current: 257/337
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.

Claims

1. A semiconductor device, comprising:

a substrate;

a dielectric layer disposed on the substrate, wherein the dielectric layer has a trench; and

an aluminum layer completely filled into the trench, wherein a reflectivity of the aluminum layer is substantially greater than 1.

2. The semiconductor device according to claim 1, further comprising at least a barrier layer disposed between the dielectric layer and the aluminum layer.

3. The semiconductor device according to claim 2, wherein the barrier layer comprises Ti/TiN or Ta/TaN.

4. The semiconductor device according to claim 1, wherein the semiconductor device is a transistor and the aluminum layer is a part of the gate of the transistor.

5. The semiconductor device according to claim 4, wherein the transistor further comprises a gate dielectric layer disposed between the aluminum layer and the substrate, and a source/drain region disposed in the substrate at two sides of the aluminum layer.