Structure and method for FinFET integrated with capacitor

• US 8,860,148 B2
• Filed: 04/11/2012
• Issued: 10/14/2014
• Est. Priority Date: 04/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Sun-Jay, Hu, Chia-Hsin
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Ahmed, Shahed
• Application Number:
  US13/444,623
• Publication Number:
  US 20130270620A1
• Time in Patent Office: 916 Days
• Field of Search: 257/401, 257/190, 257/369, 257/296, 257/E29.051, 257/E27.06, 257/E21.619, 438/151, 438/197, 438/306
• US Class Current: 257/401
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

The present disclosure provides one embodiment of a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate having a first region and a second region;

a shallow trench isolation (STI) feature formed in the semiconductor substrate, wherein the STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first thickness T1, the first portion of the STI feature being recessed from the second portion of the STI feature;

a plurality of fin active regions on the semiconductor substrate;

a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region and a portion of the second portion of the STI feature in the second region;

a plurality of dielectric features underlying the conductive features and separating the conductive feature from the fin active regions;

a first transistor disposed in the first region, wherein the first transistor comprises a first gate stack having a first one of the dielectric features and a first one of the conductive features overlying the first one of the dielectric features; and

a second transistor disposed in the second region, wherein the second transistor comprises a second gate stack having a second one of the dielectric features and a second one of the conductive features overlying the second one of the dielectric features,

wherein the first one of the dielectric features has a first dielectric thickness, and the second one of the dielectric features has a second dielectric thickness different from the first dielectric thickness.

2. The semiconductor structure of claim 1, wherein the first portion of the STI feature is recessed from the second portion of the STI feature such that a top surface of the first portion is lower than a top surface of the second portion by (T2-T1).

3. The semiconductor structure of claim 1, further comprising:

a capacitor disposed in the first region, wherein the capacitor includes one of the fin active regions, one of the conductive features, and one of the dielectric layer separating the one of the conductive features from the one of the fin active regions; and

a transistor disposed in the second region.

4. The semiconductor structure of claim 3, wherein the capacitor is a de-coupling capacitor and the transistor is a field effect transistor.

5. The semiconductor structure of claim 1, wherein the plurality of conductive features include:

a first conductive feature disposed in the first region and having a first width W1; and

a second conductive feature disposed in the second region and having a second width W2 less than the first width W1.

8. The semiconductor structure of claim 1, wherein:

each of the fin active regions extends along the first and second portions of the STI feature in a first direction; and

each of the conductive features are disposed along the fin active regions and the STI features in a second direction perpendicular to the first direction.

9. The semiconductor structure of claim 1, wherein:

the first portion of the first region has a plurality of sides; and

the second portion of the second region surrounds the first portion on each of the sides.

10. The semiconductor structure of claim 9, wherein the conductive feature that covers the first and second portions of the STI feature extends out beyond all sides of the first portion to thereby cover the portion of the second portion of the STI feature in the second region.

6. A semiconductor structure, comprising:

a semiconductor substrate having a first region and a second region;

a single fin active region formed on the semiconductor substrate that extends in the first and second regions;

a shallow trench isolation (STI) feature formed in the semiconductor substrate and adjacent the fin active region, wherein the STI feature includes;

a first portion disposed in the first region and a second portion disposed in the second region, and

the first portion of the STI feature has a first top surface and the second portion of the STI feature has a second top surface higher than the first top surface;

a first conductive feature formed on the fin active region and the STI feature, wherein the first conductive feature is disposed in the first region and covers the first portion of the STI feature, the first conductive feature further comprising a first width;

a second conductive feature formed on the fin active region and the STI feature, wherein the second conductive feature is disposed in the second region, the second conductive feature further comprising a second width less than the first width;

a first dielectric feature aligned with the first conductive feature and underlying the first conductive feature, the first dielectric feature comprising a first thickness;

a second dielectric feature aligned with the second conductive feature and underlying the second conductive feature, the second dielectric feature comprising a second thickness different from the first thickness;

wherein the fin active region, the first dielectric feature, and the first conductive feature are configured and coupled to form a capacitor; and

wherein the fin active region, the second dielectric feature, and the second conductive feature are configured and coupled to form a field effect transistor.

7. The semiconductor structure of claim 6, wherein:

the fin active region is oriented in a first direction; and

the first and second conductive features are oriented in a second direction perpendicular to the first direction.

11. A semiconductor structure, comprising:

a semiconductor substrate having a first region and a second region;

a shallow trench isolation (STI) feature formed in the semiconductor substrate, wherein the STI feature comprises a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first thickness T1, the first portion of the STI feature being recessed from the second portion of the STI feature;

a plurality of fin active regions on the semiconductor substrate;

a plurality of conductive features disposed on the fin active regions and the STI feature,

wherein one of the conductive features covers the first portion of the STI feature in the first region and a portion of the second portion of the STI feature in the second region;

wherein the plurality of conductive features further comprise;

a first conductive feature disposed in the first region and having a first width W1; and

a second conductive feature disposed in the second region and having a second width W2 less than the first width W1; and

a plurality of dielectric features underlying the conductive features and separating the conductive feature from the fin active regions, wherein the plurality of dielectric features comprise;

a first dielectric feature disposed in the first region, underlying the first conductive feature, and having a first dielectric material; and

a second dielectric feature disposed in the second region, underlying the second conductive feature, and having a second dielectric material different from the first dielectric material.

12. The semiconductor structure of claim 11, wherein:

the first conductive feature, the first dielectric feature, and a first subset of the fin active regions are configured to form a capacitor; and

the second conductive feature, the second dielectric feature, and a second subset of the fin active regions are configured to form a fin field effect transistor (FinFET).

13. A semiconductor structure, comprising:

a semiconductor substrate having a first region and a second region;

a single fin active region formed on the semiconductor substrate that extends in the first and second regions;

a shallow trench isolation (STI) feature formed in the semiconductor substrate and adjacent the fin active region, wherein the STI feature comprises;

a first portion disposed in the first region and a second portion disposed in the second region, and

the first portion of the STI feature has a first top surface and the second portion of the STI feature has a second top surface higher than the first top surface;

a first conductive feature formed on the fin active region and the STI feature, wherein the first conductive feature is disposed in the first region and covers the first portion of the STI feature, the first conductive feature further comprising a first width;

a second conductive feature formed on the fin active region and the STI feature, wherein the second conductive feature is disposed in the second region, the second conductive feature further comprising a second width less than the first width;

a first dielectric feature aligned with the first conductive feature and underlying the first conductive feature, the first dielectric feature further comprising a first dielectric material;

a second dielectric feature aligned with the second conductive feature and underlying the second conductive feature, the second dielectric feature further comprising a second dielectric material different from the first dielectric material;

wherein the fin active region, the first dielectric feature, and the first conductive feature are configured and coupled to form a capacitor; and

wherein the fin active region, the second dielectric feature, and the second conductive feature are configured and coupled to form a field effect transistor.