Thin film resistor structure

• US 8,860,181 B2
• Filed: 03/07/2012
• Issued: 10/14/2014
• Est. Priority Date: 03/07/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wei, Ming-Te, Tsao, Po-Chao, Tsai, Chen-Hua, Chen, Chien-Yang, Liang, Chia-Jui, Chen, Ming-Tsung
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/413,669
• Publication Number:
  US 20130234292A1
• Time in Patent Office: 951 Days
• Field of Search: 257/536, 257/585, 257/750, 257/E21.579, 438/662, 438/686, 438/782
• US Class Current: 257/536
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.

Claims

1. A thin film resistor structure, comprising:

a substrate;

a flat bottom ILD (inter layer dielectric) disposed on the substrate;

a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD;

a flat top ILD disposed on the bottom ILD;

a plurality of second contact disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD;

a thin film resistor disposed between the bottom ILD and the top ILD;

a stop layer disposed between the bottom ILD and the top ILD, the thin film resistor being disposed on the stop layer; and

at least one second contact penetrating through the thin film resistor and touching the surface of the stop layer.

2. The thin film resistor structure of claim 1, further comprising a protective layer disposed on the thin film resistor, wherein the area of the protect layer is the same as the area of the thin film resistor, and each sidewall of the protective layer is trimmed with each sidewall of the thin film resistor layer.

3. The thin film resistor structure of claim 1, wherein the substrate further comprises a semiconductor region and a resistor region, and the thin film resistor is disposed in the resistor region.

4. The thin film resistor structure of claim 3, further comprising at least one shallow trench isolation (STI) in the substrate within the resistor region.

5. The thin film resistor structure of claim 3, wherein the semiconductor region further comprises at least one metal gate and at least one first contact.

6. The thin film resistor structure of claim 5, wherein a top surface of the metal gate is on the same level as a top surface of the bottom ILD.

7. The thin film resistor structure of claim 5, wherein the first contact comprises a slot contact.

8. The thin film resistor structure of claim 1, further comprising at least an IMD (intermetal layer) disposed on the bottom ILD, and at least a metal trace and a via plug in the IMD.

9. A thin film resistor structure, comprising:

a substrate;

a flat bottom ILD (inter layer dielectric) disposed on the substrate;

a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD;

a flat top ILD disposed on the bottom ILD;

a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD;

a thin film resistor disposed between the bottom ILD and the top ILD;

a stop layer disposed between the bottom ILD and the top ILD, the thin film resistor being disposed on the stop layer;

at least one second contact penetrating through the thin film resistor and touching the surface of the stop layer; and

at least a first contact disposed under the thin film resistor within the bottom ILD.

10. The thin film resistor structure of claim 9, wherein the substrate further comprising a semiconductor region and a resistor region, and the thin film resistor is disposed in the resistor region.

11. The thin film resistor structure of claim 10, wherein the substrate further comprises at least a shallow trench isolation (STI) within the resistor region and the support material is disposed on the STI.

12. The thin film resistor structure of claim 9, wherein the support material comprises at least a metal gate or at least a first contact.

13. The thin film resistor structure of claim 9, wherein the supporting material extends along a first direction, the thin film resistor extends along a second direction, and the first direction is different from the second direction.

14. The thin film resistor structure of claim 9, wherein the first direction and second direction are orthogonal.

15. The thin film resistor structure of claim 9, further comprising at least one metal gate structure disposed under the thin film resistor within the bottom ILD.