Semiconductor substrate, semiconductor device, and manufacturing methods thereof

• US 8,860,183 B2
• Filed: 06/09/2010
• Issued: 10/14/2014
• Est. Priority Date: 06/10/2009
• Status: Active Grant

• Current Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Inventors: Sakai, Shiro
• Primary Examiner(s): SANDVIK, BENJAMIN P
• Application Number:
  US12/801,455
• Publication Number:
  US 20100314717A1
• Time in Patent Office: 1,588 Days
• Field of Search: None
• US Class Current: 257/615
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02642 Mask materials other than SiO2 or SiN
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 33/0066 with a substrate not being a III-V compound
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous

Abstract

The present invention provides a method of manufacturing a semiconductor substrate that includes a substrate, a first semiconductor layer arranged on the substrate, a metallic material layer arranged on the first semiconductor layer, a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer, and a cavity formed in the first semiconductor layer under the metallic material layer.

Claims

1. A semiconductor substrate, comprising:

a substrate;

a first semiconductor layer arranged on the substrate;

a metallic material layer arranged on a first portion of the first semiconductor layer;

a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer; and

a cavity formed in the first portion of the first semiconductor layer directly under the metallic material layer along a line perpendicular to the plane of the substrate,

wherein the second semiconductor layer directly contacts a second portion of the first semiconductor layer,

wherein the metallic material layer comprises titanium or chromium, and

wherein the first semiconductor layer comprises nitrogen.

2. The semiconductor substrate of claim 1, wherein the metallic material layer comprises a metallic material having a higher melting point than a heating temperature at which the second semiconductor layer is formed.

3. The semiconductor substrate of claim 1, wherein the metallic material layer comprises an oxide film.

4. The semiconductor substrate of claim 3, wherein a plurality of holes penetrates the metallic material layer.

5. The semiconductor substrate of claim 1, wherein the metallic material comprises a titanium (Ti) layer that is about 50 nm thick.

6. The semiconductor substrate of claim 1, wherein the metallic material layer comprises a chromium (Cr) layer that is 23 to 50 nm thick.

7. The semiconductor substrate of claim 1, wherein the substrate comprises a sapphire substrate or a silicon substrate.

8. A semiconductor substrate, comprising:

a semiconductor layer comprising a first side comprising recessed regions;

a plurality of metallic layers spaced apart from each other and arranged in the recessed regions; and

a cavity formed in a first portion of the semiconductor layer directly under at least one of the metallic material layers along a line perpendicular to the plane of the substrate,

each metallic layer of the plurality of metallic layers comprising a hole that penetrates the metallic layer,

wherein the semiconductor layer further comprises a second side opposite the first side, the second side being free of recessed regions, and

wherein the semiconductor layer comprises nitrogen.

9. The semiconductor substrate of claim 8, wherein the plurality of metallic layers and the first side of the semiconductor layer together form a flattened surface.

10. The semiconductor substrate of claim 9, wherein the plurality of metallic layers each comprise a tantalum (Ta) layer having a thickness in a range of 5 to 100 nm.

11. The semiconductor substrate of claim 9, wherein the plurality of metallic layers each comprise a titanium (Ti) layer having a thickness of about 50 nm.

12. The semiconductor substrate of claim 9, wherein the plurality of metallic layers each comprise a chromium (Cr) layer having a thickness in a range of 23 to 50 nm.

13. The semiconductor substrate of claim 9, wherein the plurality of metallic layers are spaced apart from each other at a constant distance.

14. The semiconductor substrate of claim 13, wherein the constant distance is 5 μ

m.

15. The semiconductor substrate of claim 9, wherein each metallic layer of the plurality of metallic layers is stripe shaped.

16. The semiconductor substrate of claim 15, wherein the stripe shaped metallic layers each have a width of 5 μ

m.

17. The semiconductor substrate of claim 9, wherein recessed regions are recessed to a depth in a range of 5 to 100 nm.

18. The semiconductor substrate of claim 9, wherein recessed regions are recessed to a depth in a range of about 50 nm.

19. The semiconductor substrate of claim 9, wherein recessed regions are recessed to a depth in a range of 23 to 50 nm.

20. A method of manufacturing a semiconductor substrate, the method comprising:

forming a first semiconductor layer on a substrate;

forming a metallic material layer on the first semiconductor layer;

forming a second semiconductor layer directly on the first semiconductor layer and the metallic material layer; and

forming a cavity in a portion of the first semiconductor layer directly under the metallic material layer along a line perpendicular to the plane of the substrate,

wherein the metallic material layer comprises titanium or chromium, and

wherein the first semiconductor layer comprises nitrogen.

21. The method of claim 20, wherein the metallic material layer comprises a plurality of stripe-shaped portions spaced apart from each other by a constant distance, the stripe-shaped portions comprising a constant width, and the second semiconductor layer is at least 0.5 times as thick as a width of a first stripe-shaped portion of the metallic material layer.

22. The method of claim 20, wherein the metallic material layer comprises an oxide film, the oxide film forming a mask for the first semiconductor layer.

23. The method of claim 22, wherein a plurality of holes penetrates the metallic material layer.

24. The method of claim 20, wherein the second semiconductor layer is formed by metal organic chemical vapor deposition, and a portion of the first semiconductor layer, on which the metallic material layer is not formed, is grown toward the second semiconductor layer.

25. The method of claim 24, wherein the first semiconductor layer and the second semiconductor layer comprise the same semiconductor material, and the metallic material layer comprises a metallic material having a higher melting point than the heating temperature at which the second semiconductor layer is formed.

26. The method of claim 25, wherein the metallic material layer comprises a plurality of holes and an oxide film that forms a mask for the first semiconductor layer, and the plurality of holes is connected to the first semiconductor layer and the second semiconductor layer,

wherein the second semiconductor layer is formed using a metal organic chemical vapor deposition technique, and

wherein a portion of the first semiconductor layer under the metallic material layer reacts with the metallic material layer and oxygen, the portion of the first semiconductor layer is evaporated from the plurality of holes to form the cavity.

27. The method of claim 20, wherein the metallic material layer comprises Ti and is about 50 nm thick.

28. The method according to claim 20, wherein the metallic material layer comprises Cr and is 23 to 50 nm thick.