Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package

• US 8,860,195 B2
• Filed: 08/03/2009
• Issued: 10/14/2014
• Est. Priority Date: 12/15/2005
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lam, Ken M.
• Primary Examiner(s): Lee, Jae
• Application Number:
  US12/534,819
• Publication Number:
  US 20090294957A1
• Time in Patent Office: 1,898 Days
• Field of Search: 257/678, 257/723, 257/724
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An apparatus and method for incorporating discrete passive components into an integrated circuit package. A first surface of a substrate is coated with a material to mechanically protect the first surface. A first metal layer and then an insulating layer are formed on a second surface of the substrate. Selected areas are removed from the insulating and a second metal layer is formed over the insulating layer and the exposed metal layer. Selected areas of the second metal layer are removed to form a plurality of structures, including at least one of a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached. An electronic component may be attached to at least one of the structures. The resulting integrated circuit die may be incorporated into an electronic package.

Claims

1. An electronic package comprising:

a package substrate including a top surface;

an integrated circuit die attached to the top surface of the package substrate, the integrated circuit die including a device substrate having a first and second surface, the first surface facing the top surface of the package substrate and having a passivation layer formed thereon;

a metal layer formed directly on the second surface of the device substrate;

a first structure formed on the metal layer;

a first electronic component attached to the first structure

a second structure formed on the metal layer;

a second electronic component attached to the second structure and coupled to the top surface of the package substrate by a wirebond; and

a third structure formed on the metal layer, the third structure electrically coupled to at least one of the first and second electronic components.

2. The electronic package of claim 1 wherein the third structure comprises at least one of a wirebonding pad, a solder-bonding pad and a device interconnect circuit.

3. The electronic package of claim 1 wherein the second electronic component is one of an active component or a passive component.

4. The electronic package of claim 1 wherein the electronic package is a multichip module package.

5. The electronic package of claim 1 wherein the package substrate is a printed circuit board.

6. The electronic package of claim 1 wherein the integrated circuit die is a flip chip.

7. A method of integrated circuit device packaging comprising:

fabricating an integrated circuit die from a device substrate having a first surface and a second surface, the fabricating comprising;

forming a passivation layer on the first surface of the device substrate

forming a metal layer directly on the second surface of the device substrate;

forming at least one structure on the metal layer;

attaching at least one second electronic component to the at least one structure formed on the metal layer; and

singulating the device substrate so that the integrated circuit die includes the at least the one structure with the attached at least one second electronic component; and

attaching the integrated circuit die to a package substrate by coupling the passivation layer of the integrated circuit die to the top surface of the package substrate, wherein the passivation layer of the integrated circuit die faces the top surface of the package substrate.

8. The method of claim 7 wherein the passivation layer of the integrated circuit die is coupled to the top surface of the package substrate by solder balls.

9. The method of claim 7 further comprising coupling the at least one second electronic component to the package substrate.

10. The method of claim 7 wherein the at least one second electronic component is coupled to the package substrate by a wirebond.

11. The method of claim 7 wherein the at least one second electronic component is one of an active or a passive component.

12. The method of claim 7 wherein the package substrate is a printed circuit board.

13. The method of claim 7 wherein the at least one structure formed on the metal layer comprises at least one of a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which the at least one second electronic component is attached.