Techniques for adjusting gears of an oscillator

• US 8,860,482 B1
• Filed: 06/14/2013
• Issued: 10/14/2014
• Est. Priority Date: 06/14/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Liu, Xiong, Tran, Thungoc, Hoang, Tim Tri, Wong, Wilson
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/918,739
• Time in Patent Office: 487 Days
• Field of Search: 327/148, 327/157
• US Class Current: 327/157
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase-locked loop circuit includes an oscillator circuit that generates a clock signal. The oscillator circuit has gears. Each of the gears of the oscillator circuit corresponds to a respective frequency range of the clock signal. A gear control circuit includes a regulator circuit that provides a supply voltage to the oscillator circuit. Each of the gears of the oscillator circuit corresponds to a different supply voltage provided by the regulator circuit. The regulator circuit varies the supply voltage to change a selected one of the gears of the oscillator circuit. The gear control circuit varies the supply voltage for one of the gears of the oscillator circuit to adjust a frequency range of that gear of the oscillator circuit.

Claims

1. A circuit comprising:

a phase-locked loop circuit comprising an oscillator circuit to generate a first clock signal, wherein the oscillator circuit comprises gears, and wherein each of the gears of the oscillator circuit corresponds to a different frequency range of the first clock signal; and

a gear control circuit comprising a regulator circuit to provide a supply voltage to the oscillator circuit, wherein each of the gears of the oscillator circuit corresponds to a different supply voltage provided by the regulator circuit, wherein the regulator circuit varies the supply voltage to change a selected one of the gears of the oscillator circuit, and wherein the gear control circuit varies the supply voltage for a first one of the gears of the oscillator circuit to adjust overlap between a frequency range of the first one of the gears of the oscillator circuit and a frequency range of a second one of the gears of the oscillator circuit.

2. The circuit of claim 1, wherein the gear control circuit determines minimum and maximum frequencies of the first clock signal for the first one of the gears of the oscillator circuit, and wherein the gear control circuit compares the minimum and the maximum frequencies of the first clock signal to respective ideal minimum and maximum frequencies of the first clock signal for the first one of the gears of the oscillator circuit to generate a frequency difference.

3. The circuit of claim 2, wherein the gear control circuit causes the regulator circuit to vary the supply voltage for the first one of the gears of the oscillator circuit to adjust the frequency range of the first one of the gears of the oscillator circuit based on the frequency difference.

4. The circuit of claim 3, wherein the oscillator circuit varies a frequency of the first clock signal in response to changes in a control voltage, and wherein the gear control circuit further comprises a detector circuit that compares the control voltage to first and second threshold voltages to generate an indication of when the control voltage is within a voltage range defined by the first and the second threshold voltages.

7. The circuit of claim 3, wherein the gear control circuit further comprises a frequency detector circuit that compares a second clock signal that is generated based on the first clock signal to a third clock signal to generate an indication of a frequency difference between the second and the third clock signals, and wherein the gear control circuit determines the minimum and the maximum frequencies of the first clock signal for the first one of the gears of the oscillator circuit based on the indication of the frequency difference between the second and the third clock signals generated by the frequency detector circuit.

8. The circuit of claim 7, wherein the phase-locked loop circuit further comprises a phase frequency detector circuit coupled to a charge pump circuit, wherein the oscillator circuit varies a frequency of the first clock signal in response to changes in a control voltage generated by the charge pump circuit when the charge pump circuit is enabled, and wherein the charge pump circuit is disabled and the control voltage is forced to predetermined voltages for the gear control circuit to determine the minimum and the maximum frequencies of the first clock signal for the first one of the gears of the oscillator circuit.

5. A circuit comprising:

a phase-locked loop circuit comprising an oscillator circuit to generate a first clock signal, wherein the oscillator circuit comprises gears;

a gear control circuit comprising a regulator circuit to provide a supply voltage to the oscillator circuit, wherein each of the gears of the oscillator circuit corresponds to a supply voltage provided by the regulator circuit and to a frequency range of the first clock signal; and

a detector circuit that generates an indication of when the phase-locked loop circuit is in lock, wherein the gear control circuit determines frequencies of the first clock signal based on the indication of when the phase-locked loop circuit is in lock, and wherein the gear control circuit causes the regulator circuit to vary the supply voltage for one of the gears of the oscillator circuit to adjust a frequency range of the one of the gears of the oscillator circuit based on the frequencies determined for the first clock signal.

6. The circuit of claim 5, wherein the phase-locked loop circuit further comprises a frequency divider circuit that generates a second clock signal based on the first clock signal, wherein the frequency divider circuit causes a frequency of the second clock signal to have the frequency of the first clock signal divided by a frequency division value, wherein the oscillator circuit varies the frequency of the first clock signal in response to a control voltage, and wherein the gear control circuit varies the control voltage by changing the frequency division value of the frequency divider circuit.

9. A circuit comprising:

a phase-locked loop circuit comprising an oscillator circuit that generates a first clock signal, wherein the oscillator circuit comprises gears, and wherein each of the gears of the oscillator circuit corresponds to a different frequency range of the first clock signal within a tuning range of the oscillator circuit; and

a gear control circuit comprising a regulator circuit that provides a supply voltage to the oscillator circuit, wherein each of the gears of the oscillator circuit is generated in response to a different supply voltage provided by the regulator circuit, wherein the regulator circuit changes a selected one of the gears of the oscillator circuit by varying the supply voltage,

wherein the gear control circuit determines a frequency of the first clock signal in a first one of the gears of the oscillator circuit, wherein the gear control circuit compares the frequency of the first clock signal determined for the first one of the gears to a respective ideal frequency of the first clock signal for the first one of the gears to generate a frequency difference, and wherein the gear control circuit varies the supply voltage for the first one of the gears to adjust a frequency range of the first one of the gears based on the frequency difference.

10. The circuit of claim 9, wherein the oscillator circuit varies the frequency of the first clock signal based on a control voltage, and wherein the gear control circuit further comprises:

an under and over range detector circuit to compare the control voltage to first and second threshold voltages to generate a comparison output;

a frequency detector circuit to generate a frequency detection output based on a frequency difference between a second clock signal and a third clock signal, wherein the second clock signal is generated based on the first clock signal; and

a multiplexer circuit coupled to the frequency detector circuit and to the under and over range detector circuit.

11. The circuit of claim 10, wherein the gear control circuit further comprises:

a second control circuit, wherein the multiplexer circuit provides a value of the comparison output to the second control circuit during a closed loop adjustment mode, and wherein the multiplexer circuit provides a value of the frequency detection output to the second control circuit during an open loop adjustment mode.

12. The circuit of claim 11, wherein the phase-locked loop circuit further comprises:

a frequency divider circuit to generate the second clock signal based on the first clock signal;

a phase frequency detector circuit to generate a phase error signal based on a phase difference between the second clock signal and the third clock signal; and

a charge pump circuit to generate the control voltage based on the phase error signal, wherein the charge pump circuit is enabled during the closed loop adjustment mode, and wherein the charge pump circuit is disabled during the open loop adjustment mode.

13. The circuit of claim 11, wherein the phase-locked loop circuit further comprises:

a lock detector circuit to generate a lock signal indicating when the phase-locked loop circuit is in lock,

wherein the gear control circuit determines the frequency of the first clock signal in the first one of the gears of the oscillator circuit based on the lock signal as the control voltage varies between voltages indicated by the first and the second threshold voltages during the closed loop adjustment mode.

14. The circuit of claim 13, wherein the phase-locked loop circuit further comprises:

a frequency divider circuit to cause a frequency of the second clock signal to equal the frequency of the first clock signal divided by a frequency division value, and wherein the gear control circuit varies the control voltage between voltages indicated by the first and the second threshold voltages by changing the frequency division value of the frequency divider circuit.

15. The circuit of claim 12, wherein the gear control circuit determines the frequency of the first clock signal in the first one of the gears of the oscillator circuit based on the frequency detection output during the open loop adjustment mode, and

wherein the control voltage is forced to a predetermined voltage for the gear control circuit to determine the frequency of the first clock signal in the first one of the gears of the oscillator circuit during the open loop adjustment mode.

16. A method comprising:

generating a first clock signal using an oscillator circuit in a phase-locked loop circuit, wherein the oscillator circuit comprises gears, and wherein each of the gears of the oscillator circuit corresponds to a respective frequency range of the first clock signal within a tuning range of the oscillator circuit;

providing a supply voltage to the oscillator circuit using a regulator circuit in a gear control circuit, wherein each of the gears of the oscillator circuit is generated in response to a different supply voltage provided by the regulator circuit;

varying the supply voltage to change a selected one of the gears of the oscillator circuit; and

varying the supply voltage for a first one of the gears of the oscillator circuit using the gear control circuit to adjust overlap between a frequency range of the first one of the gears of the oscillator circuit and a frequency range of a second one of the gears of the oscillator circuit.

17. The method of claim 16, wherein varying the supply voltage for a first one of the gears of the oscillator circuit using the gear control circuit to adjust overlap between a frequency range of the first one of the gears of the oscillator circuit and a frequency range of a second one of the gears of the oscillator circuit further comprises:

determining a frequency of the first clock signal for the first one of the gears of the oscillator circuit;

comparing the frequency of the first clock signal determined for the first one of the gears to an ideal frequency of the first clock signal for the first one of the gears to generate a frequency difference; and

varying the supply voltage for the first one of the gears of the oscillator circuit using the gear control circuit to adjust the frequency range of the first one of the gears based on the frequency difference.

18. The method of claim 17, wherein determining a frequency of the first clock signal for the first one of the gears of the oscillator circuit comprises:

varying a control voltage between first and second threshold voltages during a closed loop adjustment mode, wherein the oscillator circuit varies the frequency of the first clock signal in response to changes in the control voltage,

generating a lock signal indicating when the phase-locked loop circuit is in lock using a first detector circuit in the gear control circuit, and

determining the frequency of the first clock signal for the first one of the gears of the oscillator circuit based on the lock signal.

19. The method of claim 18, wherein determining a frequency of the first clock signal for the first one of the gears of the oscillator circuit further comprises:

comparing the control voltage to the first and the second threshold voltages to generate an indication of when the control voltage is within a voltage range defined by the first and the second threshold voltages using a second detector circuit in the gear control circuit.

20. The method of claim 17, wherein determining a frequency of the first clock signal for the first one of the gears of the oscillator circuit comprises:

generating a frequency detection signal based on a frequency difference between a second clock signal and a third clock signal, wherein the second clock signal is generated based on the first clock signal, and wherein the oscillator circuit varies the frequency of the first clock signal in response to changes in a control voltage; and

forcing the control voltage to a predetermined voltage for the gear control circuit to determine the frequency of the first clock signal for the first one of the gears of the oscillator circuit based on the frequency detection signal during an open loop adjustment mode.