Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

• US 8,860,485 B2
• Filed: 04/01/2013
• Issued: 10/14/2014
• Est. Priority Date: 11/20/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Koyama, Jun
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US13/854,176
• Publication Number:
  US 20130222033A1
• Time in Patent Office: 561 Days
• Field of Search: 327199-203, 327/208, 327210-212, 327/218, 327/219
• US Class Current: 327/215
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/286 bistable
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H03K 3/356173 with synchronous operation

Abstract

To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

Claims

1. A latch circuit comprising:

a latch portion; and

a data holding portion for holding data of the latch portion,

the latch portion comprising;

a first element; and

a second element,

wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, and

wherein the input of the first element is electrically connected to a first wiring configured to be supplied with an input signal, and the output of the first element is electrically connected to a second wiring configured to be supplied with an output signal,

the data holding portion comprising;

a transistor;

a capacitor; and

an inverter,

wherein a channel formation region of the transistor includes an oxide semiconductor layer,

wherein an input of the inverter is electrically connected to the capacitor,

wherein the inverter includes an n-channel transistor and a p-channel transistor, and

wherein the oxide semiconductor layer contains indium, gallium, and zinc.

2. The latch circuit according to claim 1,

wherein one of a source and a drain of the transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the transistor is electrically connected to one of electrodes of the capacitor and an input of the inverter, and

wherein an output of the inverter is electrically connected to the first wiring.

3. The latch circuit according to claim 1, wherein the transistor controls writing of data into a gate capacitor of the inverter.

4. The latch circuit according to claim 1, wherein the transistor has a function of holding data in a gate capacitor of the inverter.

5. The latch circuit according to claim 1, wherein the transistor controls writing of data into the capacitor.

6. The latch circuit according to claim 1, wherein the transistor has a function of holding data in the capacitor.

7. The latch circuit according to claim 1, wherein the first element is a NAND, and the second element is a clocked inverter.

8. A latch circuit comprising:

a latch portion; and

a data holding portion for holding data of the latch portion,

the latch portion comprising;

a first inverter; and

a second inverter,

wherein an output of the first inverter is electrically connected to an input of the second inverter, and an output of the second inverter is electrically connected to an input of the first inverter, and

wherein the input of the first inverter is electrically connected to a first wiring configured to be supplied with an input signal, and the output of the first inverter is electrically connected to a second wiring configured to be supplied with an output signal,

the data holding portion comprising;

a transistor;

a capacitor; and

a third inverter,

wherein a channel formation region of the transistor includes an oxide semiconductor layer,

wherein an input of the third inverter is electrically connected to the capacitor,

wherein the third inverter includes an n-channel transistor and a p-channel transistor, and

wherein one of a source and a drain of the transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the transistor is electrically connected to the input of the third inverter, and

wherein an output of the third inverter is electrically connected to the first wiring.

9. The latch circuit according to claim 8, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

10. The latch circuit according to claim 8, wherein the transistor controls writing of data into a gate capacitor of the third inverter.

11. The latch circuit according to claim 8, wherein the transistor has a function of holding data in a gate capacitor of the third inverter.

12. A circuit comprising:

a first element;

a second element;

a first transistor;

a second transistor; and

a capacitor,

wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, and

wherein the input of the first element is electrically connected to a first wiring configured to be supplied with an input signal, and the output of the first element is electrically connected to a second wiring configured to be supplied with an output signal,

wherein a channel formation region of the first transistor includes an oxide semiconductor layer, and

wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor and a gate of the second transistor, and

wherein one of a source and a drain of the second transistor is electrically connected to the first wiring.

13. The circuit according to claim 12, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

14. The circuit according to claim 12, wherein the first transistor controls writing of data into the capacitor.

15. The circuit according to claim 12, wherein the first transistor has a function of holding data in the capacitor.

16. The circuit according to claim 12, wherein the first element is a NAND, and the second element is a clocked inverter.

17. The circuit according to claim 12, further comprising a switch between the first element and the first wiring.

18. The circuit according to claim 12, further comprising a switch between the second element and the first wiring.

19. The circuit according to claim 12, further comprising a switch between the one of the source and the drain of the second transistor and the first wiring.