Supply voltage generating circuit

• US 8,860,499 B2
• Filed: 06/07/2013
• Issued: 10/14/2014
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: PS4 Luxco S.a.r.l.
• Inventors: Hayashi, Koichiro, Tanaka, Hitoshi
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US13/912,845
• Publication Number:
  US 20130265103A1
• Time in Patent Office: 494 Days
• Field of Search: None
• US Class Current: 327/536
• CPC Class Codes: G05F 1/62 using bucking or boosting dc sources
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.

Claims

1. A semiconductor device comprising:

first and second voltage terminals to be respectively supplied with first and second voltages different from each other;

an internal voltage node;

a switching circuit coupled between the first and second voltage terminals and the internal voltage node, the switching circuit to take either one of a first switching state in which the first voltage terminal and the internal voltage node are connected and a second switching state in which the second voltage terminal and the internal voltage node are connected; and

a voltage booster circuit including a voltage output node and first and second boosting circuits each including a capacitor and each coupled to the internal voltage node, the voltage booster circuit being configured such that the first and second voltage boosting circuits are coupled in series to the voltage output node when the switching circuit takes the first switching state and that the first boosting circuit is coupled to the voltage output node and the second boosting circuit is disconnected from each of the first boosting circuit and the voltage output node when the switching circuit takes the second switching state, and

at least when the switching circuit takes a switching state, the capacitor of the first boosting circuit is coupled to the voltage output node and the capacitor of the second boosting circuit is disconnected from each of the voltage output node and the capacitor of the first boosting circuit.

2. The semiconductor device as claimed in claim 1, further comprising a first external voltage terminal to be supplied with the first voltage, the first external voltage terminal coupled to the first voltage terminal.

3. The semiconductor device as claimed in claim 2, further comprising a second external voltage terminal to be supplied with a third voltage and an internal voltage generator coupled to the second external voltage terminal to also be supplied with the third voltage and configured to generate the second voltage at the second voltage terminal.

4. The semiconductor device as claimed in claim 3, wherein the third voltage is greater than the first voltage.

5. The semiconductor device as claimed in claim 4, wherein the third voltage is greater than the second voltage.

6. The semiconductor device as claimed in claim 1, wherein the second boosting circuit is configured to boost the first voltage supplied with the internal voltage node to generate a first boosting voltage and the first boosting circuit is configured to boost the first boosting voltage to generate at the voltage output node a second boosting voltage when the switching circuit takes the first switching state.

7. The semiconductor device as claimed in claim 6, wherein the first boosting circuit is configured to boost the second voltage supplied with the internal voltage node to generate at the voltage output node a third boosting voltage when the switching circuit takes the second switching state.

8. A method for generating a supply voltage, comprising:

providing, from a first voltage terminal and a second voltage terminal, first voltage and second voltage different from each other;

selecting, by a switching circuit coupled between the first voltage terminal and the second voltage terminal, either one of a first switching state in which the first voltage terminal and an internal voltage node are connected and a second switching state in which the second voltage terminal and the internal voltage node are connected; and

outputting, by a voltage booster circuit including first boosting circuit and second boosting circuit, either one of a first boosted voltage generated by coupling the first boosting circuit and the second boosting circuit in series to a voltage output node at the first switching state and a second boosted voltage generated by coupling the first boosting circuit to the voltage output node and disconnecting the second boosting circuit from each of the first boosting circuit and the voltage output node at the second switching state, and

the first and second boosting circuits being such that, at least when the switching circuit takes a switching state, a capacitor of the first boosting circuit is coupled to the voltage output node and a capacitor of the second boosting circuit is disconnected from each of the voltage output node and the capacitor of the first boosting circuit.

9. The method of claim 8, further comprising a first external voltage terminal to be supplied with the first voltage, the first external voltage terminal coupled to the first voltage terminal.

10. The method of claim 9, further comprising a second external voltage terminal to be supplied with a third voltage and an internal voltage generator coupled to the second external voltage terminal to also be supplied with the third voltage and configured to generate the second voltage at the second voltage terminal.

11. The method of claim 10, wherein the third voltage is greater than the first voltage.

12. The method of claim 11, wherein the third voltage is greater than the second voltage.

13. The method of claim 8, wherein the second boosting circuit is configured to boost the first voltage supplied with the internal voltage node to generate a first boosting voltage and the first boosting circuit is configured to boost the first boosting voltage to generate at the voltage output node a second boosting voltage when the switching circuit takes the first switching state.

14. The method of claim 13, wherein the first boosting circuit is configured to boost the second voltage supplied with the internal voltage node to generate at the voltage output node a third boosting voltage when the switching circuit takes the second switching state.