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Hardware de-convolution block for multi-phase scanning

  • US 8,860,682 B1
  • Filed: 09/11/2013
  • Issued: 10/14/2014
  • Est. Priority Date: 04/22/2013
  • Status: Active Grant
First Claim
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1. A processing device comprising:

  • a memory device configured to store a capacitance map comprising convolved capacitance data, wherein the convolved data is a result of multi-phase transmit (TX) scanning of a sense array with a plurality of TX patterns, the scanning of the sense array with each of the plurality of TX patterns including simultaneously driving different phases of a signal on the sense array; and

    a de-convolution circuit block coupled to the memory device, wherein the de-convolution circuit block is configured to de-convolve the convolved capacitance data with inverses of the plurality of TX patterns to obtain capacitance data for a de-convolved capacitance map.

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