Nonvolatile semiconductor memory device

• US 8,861,275 B2
• Filed: 12/05/2013
• Issued: 10/14/2014
• Est. Priority Date: 11/29/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Maeda, Takashi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/098,237
• Publication Number:
  US 20140092684A1
• Time in Patent Office: 313 Days
• Field of Search: 365/185.17, 365/185.05, 365/185.25, 365/185.23
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a memory cell array including a first block, the first block including a first memory string, the first memory string including a memory cell, a first transistor, a second transistor, and a third transistor, the first transistor being electrically connected to the second transistor, the second transistor being electrically connected to the memory cell;

a row decoder including a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the row decoder being configured to apply a first voltage to gates of the fourth transistor and the fifth transistor when the first block is selected, a first end of the fourth transistor and a first end of the fifth transistor being electrically connected to a first node, both a second end of the fourth transistor and a first end of the sixth transistor being electrically connected to a gate of the first transistor, a second end of the sixth transistor being electrically connected to a second node, the second node being different from the first node, both a second end of the fifth transistor and a first end of the seventh transistor electrically connected to a gate of the second transistor, a second end of the seventh transistor being electrically connected to a third node, the third node being different from both the first node and the second node, gates of the six transistor and the seventh transistor being electrically connected to a gate of the eighth transistor.

2. The nonvolatile semiconductor memory device according to claim 1,

wherein a first end of the eighth transistor is electrically connected to a gate of the memory cell and a second end of the eighth transistor is electrically connected to a fourth node.

3. The nonvolatile semiconductor memory device according to claim 1, further comprising;

a first circuit configured to output a first voltage and a second voltage, the second voltage being lower than the first voltage, the first circuit including a charge pump circuit.

4. The nonvolatile semiconductor memory device according to claim 2, further comprising:

a first circuit configured to output a first voltage and a second voltage, the second voltage being lower than the first voltage, the first circuit including a charge pump circuit.

5. The nonvolatile semiconductor memory device according to claim 4,

wherein the charge pump circuit includes a plurality of capacitors.

6. The nonvolatile semiconductor memory device according to claim 4,

wherein the first circuit includes a fifth node and a sixth node, the first voltage is output from the fifth node, the second voltage is output from the sixth node, the fifth node is electrically connected to the sixth node via a plurality of ninth transistors, and a gate of the ninth transistor is electrically connected to a first end of the ninth transistor.