Decision feedback equalizer, receiving circuit, and decision feedback equalization processing method

• US 8,861,582 B2
• Filed: 07/08/2011
• Issued: 10/14/2014
• Est. Priority Date: 08/04/2010
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Shibasaki, Takayuki
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): TAYONG, HELENE E
• Application Number:
  US13/178,744
• Publication Number:
  US 20120033726A1
• Time in Patent Office: 1,194 Days
• Field of Search: 375/233, 375/232, 375/316
• US Class Current: 375/233
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A decision feedback equalizer includes: L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.

Claims

1. A decision feedback equalizer comprising:

L equalization calculation circuits, L being a positive integer, to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample;

a first logic circuit to generate first M logical values, M being an integer greater than 2, by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first sample; and

a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.

2. The decision feedback equalizer according to claim 1, further comprising:

a second logic circuit having substantially the same logic as logic of the first logic circuit; and

a second selection circuit to generate second M logical values by selecting and arranging calculation values of the M calculation values based on the first M logical values, to select one of the second M logical values based on the data decision value for the fourth sample, and to output the selected logical value as a data decision value of the second sample.

3. The decision feedback equalizer according to claim 2, further comprising:

a third logic circuit having substantially the same logic as logic of the first logic circuit; and

a third selection circuit to generate third M logical values by selecting and arranging calculation values of M calculation values for a fifth sample sampled before sampling the second sample based on the second M logical values, select one of the third M logical values based on the data decision value for the fourth sample, and to output the selected logical value as a data decision value of the fifth sample.

4. The decision feedback equalizer according to claim 1, further comprising,

a data holding circuit to store at least one of the data decision values.

5. The decision feedback equalizer according to claim 1, further comprising,

a fourth selection circuit to select one of the first M calculation values based on the data decision value of the fourth sample and to output the selected calculation value as a data decision value of the third sample.

6. The decision feedback equalizer according to claim 1, further comprising,

a fifth selection circuit to select one of M calculation values of a sixth sample, which is sampled before sampling the first sample and is different from the third sample, based on the data decision value of the third sample and to output the selected calculation value as a data decision value of the sixth sample.

7. The decision feedback equalizer according to claim 1, further comprising,

a data holding circuit, provided between the logic circuit and the selection circuit, to hold the M logical values in synchronization with a clock.

8. A receiving circuit comprising:

a sampling circuit to sample receiving data in synchronization with a sampling clock;

a demultiplexing circuit to demultiplex the receiving data sampled by the sampling circuit;

a decision feedback equalizer to decide L samples of input data from the demultiplexing circuit, L being a positive integer; and

a phase adjustment circuit to adjust phase of the sampling clock based on the sampled receiving data,

wherein the decision feedback equalizer includes,

L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample, M being an integer greater than 2;

a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on data decision value for a third sample sampled before sampling the first data; and

a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.

9. The receiving circuit according to claim 8, further comprising:

a second logic circuit having substantially the same logic as logic of the first logic circuit; and

a second selection circuit to generate second M logical values by selecting and arranging calculation values of the M calculation values based on the first M logical values, to select one of the second M logical values based on the data decision value for the fourth sample, and to output the selected logical value as a data decision value of the second sample.

10. The receiving circuit according to claim 9, further comprising:

a third logic circuit having substantially the same logic as logic of the first logic circuit; and

a third selection circuit to generate third M logical values by selecting and arranging calculation values of M calculation values for a fifth sample sampled before sampling the second sample based on the second M logical values, select one of the third M logical values based on the data decision value for the fourth sample, and to output the selected logical value as a data decision value of the fifth sample.

11. The receiving circuit according to claim 8, further comprising,

a data holding circuit to store at least one of the data decision values.

12. The receiving circuit according to claim 8, further comprising,

a fourth selection circuit to select one of the first M calculation values based on the data decision value of the fourth sample and to output the selected calculation value as a data decision value of the third sample.

13. The receiving circuit according to claim 8, further comprising,

a fifth selection circuit to select one of M calculation values of a sixth sample, which is sampled before sampling the first sample and is different from the third sample, based on the data decision value of the third sample and to output the selected calculation value as a data decision value of the sixth sample.

14. The receiving circuit according to claim 8, further comprising,

a data holding circuit, provided between the logic circuit and the selection circuit, to hold the M logical values in synchronization with a clock.

15. A decision feedback equalization process method comprising:

performing an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample by using L equalization calculation circuits, M being an integer greater than 2 and L being a positive integer;

generating first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first sample by a first logic circuit;

selecting one of the M logical values based on a data decision value for a fourth sample sampled before sampling the third sample; and

outputting the selected logical value as a data decision value of the first sample.

16. The decision feedback equalization process method according to claim 15, further comprising:

generating second M logical values by selecting and arranging calculation values of the M calculation values based on the first M logical values by a second logic circuit having substantially the same logic as logic of the first logic circuit; and

selecting one of the second M logical values based on the data decision value for the fourth sample; and

outputting the selected logical value as a data decision value of the second sample.

17. The decision feedback equalization process method according to claim 16, further comprising:

generating third M logical values by selecting and arranging calculation values of M calculation values for a fifth sample sampled before the second sample based on the second M logical values by a third logic circuit having substantially the same logic as logic of the first logic circuit; and

selecting one of the third M logical values based on the data decision value for the fourth sample; and

outputting the selected logical value as a data decision value of the fifth sample.