Digital front-end circuit and method for using the same

• US 8,861,656 B2
• Filed: 07/31/2012
• Issued: 10/14/2014
• Est. Priority Date: 02/18/2010
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Hollevoet, Lieven, Naessens, Frederik, Raghavan, Praveen, Pollin, Sofie, Estraviz, Eduardo Lopez
• Primary Examiner(s): Singh, Hirdepal
• Application Number:
  US13/563,243
• Publication Number:
  US 20130022157A1
• Time in Patent Office: 805 Days
• Field of Search: 375/222, 375/259, 375/262, 375/271, 375/286, 375/295, 375/302, 375/316, 375/340, 375/343, 375/346, 375/347, 375/350
• US Class Current: 375/343
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00

Abstract

A digital front-end circuit is disclosed. In one aspect, the circuit includes a filtering block for filtering received data. The filtering block has a first filter branch for filtering the received data in a first frequency band and a second filter branch for filtering the received data in a selected second frequency band. The second filter branch is in parallel with the first filter branch, is programmable and includes a block for resampling the received data. The front-end circuit also includes a circuit for performing synchronization and spectrum sensing on the received data, which is in connection with the output of the filtering block. The front-end circuit also includes a controller block for controlling the filtering block and the synchronization circuit.

Claims

1. A digital front-end circuit comprising:

a filtering block configured to filter received data, the filtering block comprising a first filter branch for filtering the received data in a first frequency band and a second filter branch for filtering the received data in a selected second frequency band, the second frequency band being different from the first frequency band, the second filter branch being in parallel with the first filter branch, the second filter branch being programmable and comprising a resampling block for resampling the received data,

a synchronization circuit configured to perform synchronization and spectrum sensing on the received data, the circuit being in connection with the output of the filtering block; and

a controller block configured to control the filtering block and the synchronization circuit,

wherein the synchronization circuit further comprises;

a correlator block configured to correlate data output by the filtering block,

a vectorizing block configured to vectorize the data output by the correlator block or data output by the filtering block, and

a processor block connected to the vectorizing block, the processor block comprising a scalar portion and a vector portion, the scalar portion configured to exchange control instructions with vectorizing block and the vector portion, the vector portion being configured to process the vectorized data, the processor block further being configured to detect signal presence in the selected second frequency band.

2. The digital front-end circuit as in claim 1, comprising a rotation accelerator block for improved sensing.

3. The digital front-end circuit as in claim 1, further comprising an FFT accelerator configured to detect signal presence.

4. The digital front-end circuit as in claim 1, further comprising a compensation block configured to compensate impaired received data.

5. The digital front-end circuit as in claim 4, wherein the compensation block is configured to compensate DC offset and/or I/Q imbalance.

6. The digital front-end circuit as in claim 1, further comprising a receive buffer.

7. The digital front-end circuit as in claim 1, wherein the processor block comprises a clock arranged for operation at the speed of the received data.

8. The digital front-end circuit as in claim 1, wherein the processor block comprises a detection block configured to detect the signal presence in the selected second frequency band.

9. A digital receiver comprising a digital front-end circuit as in claim 1.

10. A digital receiver as in claim 9, further comprising a reconfigurable analogue front-end circuit.

11. A digital front-end structure comprising a digital front-end circuit as in claim 1, and at least one further digital front-end circuit, the at least one further digital front-end circuit comprising:

a further filtering block comprising a third filter branch for filtering the received data in the first frequency band or in a third frequency band different from the first frequency band;

a further synchronization circuit configured to perform synchronization and spectrum sensing, the further synchronization circuit being in connection with the output of the further filtering block, the further synchronization circuit comprising a further processing block and a further correlator block configured to correlate data output by the further filtering block; and

a further controller block configured to control the further filtering block and the further synchronization circuit.

12. The digital front-end structure as in claim 11, wherein the further filtering block comprises a programmable fourth filter branch in parallel with the third filter branch.

13. A digital receiver comprising a digital front-end structure as in claim 11.

14. A digital receiver as in claim 13, further comprising a reconfigurable analogue front-end circuit.