×

Clock data recovery circuit with equalizer clock calibration

  • US 8,861,667 B1
  • Filed: 07/12/2002
  • Issued: 10/14/2014
  • Est. Priority Date: 07/12/2002
  • Status: Active Grant
First Claim
Patent Images

1. An integrated circuit device comprising:

  • a sampling circuit to capture samples of a data signal from a signal path in response to a sampling clock signal;

    a feedback driver coupled to an input of the sampling circuit and adapted to output an equalizing signal onto the signal path in response to a first clock signal; and

    a clock signal generator to adjust a phase of the first clock signal to achieve phase alignment between transitions of the equalizing signal and transitions of the data signal.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×