Clock data recovery circuit with equalizer clock calibration

• US 8,861,667 B1
• Filed: 07/12/2002
• Issued: 10/14/2014
• Est. Priority Date: 07/12/2002
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Stojanovic, Vladimir M., Chen, Fred F.
• Primary Examiner(s): Dsouza, Adolf
• Application Number:
  US10/195,140
• Time in Patent Office: 4,477 Days
• Field of Search: 375/371, 375/354, 714/12, 360/51
• US Class Current: 375/371
• CPC Class Codes: H04L 25/03114 non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A signal receiving circuit having an equalizer calibration function. The signal receiving circuit includes a sampling circuit, output driver and clock signal generator. The sampling circuit captures samples of a data signal in response to a sampling clock signal. The output driver outputs an equalizing signal to an input of the sampling circuit in response to a first clock signal. The clock signal generator adjusts a phase of the first clock signal to achieve phase alignment between transitions of the equalizing signal and transitions of the data signal.

Claims

1. An integrated circuit device comprising:

a sampling circuit to capture samples of a data signal from a signal path in response to a sampling clock signal;

a feedback driver coupled to an input of the sampling circuit and adapted to output an equalizing signal onto the signal path in response to a first clock signal; and

a clock signal generator to adjust a phase of the first clock signal to achieve phase alignment between transitions of the equalizing signal and transitions of the data signal.

2. The integrated circuit device of claim 1 wherein the clock signal generator is adapted to generate the sampling clock signal and, when a control signal is in a first state, to adjust a phase of the sampling clock signal to reduce a phase difference between the sampling clock signal and transitions in the data signal.

3. The integrated circuit device of claim 2 wherein the clock signal generator is adapted to suspend adjustment of the phase of the sampling clock signal when the control signal is in a second state.

4. The integrated circuit device of claim 3 wherein the clock signal generator is adapted to adjust the phase of the first clock signal regardless of the state of the control signal such that, when the control signal is in the first state, a substantially fixed phase offset is maintained between the first clock signal and the sampling clock signal, and, when the control signal is in the second state, the phase offset between the first clock signal and the sampling clock signal is adjusted.

5. The integrated circuit device of claim 1 further comprising:

a buffer circuit to store data values that correspond to the samples of the data signal;

a signal generator to generate a predetermined sequence of values; and

a first select circuit having a first input coupled to the signal generator, a second input coupled to the buffer circuit, and an output coupled to an input of the feedback driver.

6. The integrated circuit device of claim 5 wherein the first select circuit has a control input coupled to receive the control signal, the first select circuit being adapted to output the predetermined sequence of values to the feedback driver when the control signal is in the second state, and to output a value stored within the buffer circuit to the feedback driver when the control signal is in the first state.

7. The integrated circuit device of claim 6 further comprising a second select circuit coupled between the buffer circuit and the second input of the first select circuit, the second select circuit being adapted to select one of a plurality of storage elements within the buffer circuit to output a data value to the second input of the first select circuit.

8. The integrated circuit device of claim 5 wherein the predetermined sequence of values is an alternating sequence formed by a first digital value and a second digital value.

9. The integrated circuit device of claim 1 wherein the clock signal generator comprises a phase control circuit coupled to the sampling circuit, the phase control circuit to receive the samples, the phase control circuit being adapted to generate a phase adjust signal according to whether the samples indicate one of a phase lead between a component signal of the sample clock signal and transitions in the data signal and phase lag between a component signal of the sample clock signal and transitions in the data signal.

10. The integrated circuit device of claim 9 wherein the clock signal generator comprises:

a reference loop to generate a plurality of reference clock signals having incremental phase offsets relative to one another; and

a first mix logic circuit coupled to receive the plurality of reference clock signals from the reference loop and the first mix logic coupled to receive the phase adjust signal from the phase control circuit, the first mix logic circuit being adapted to increment and decrement a phase count value in response to the phase adjust signal.

11. The integrated circuit device of claim 10 wherein the first mix logic circuit is further adapted to select a pair of the reference clock signals based on a first component of the phase count value and the first mix logic circuit adapted to generate an interpolation value based on a second component of the phase count value.

12. The integrated circuit device of claim 11 wherein the clock signal generator further comprises a first clock mixer coupled to receive the pair of the reference clock signals and the interpolation value from the first mix logic circuit, the first clock mixer being adapted to generate the sample clock signal by interpolating between the reference clock signals of the pair of the reference clock signals in accordance with the interpolation value.

13. The integrated circuit device of claim 1 wherein the first clock signal is phase advanced relative to the sampling clock signal according to a propagation delay associated with at least the feedback driver.

14. The integrated circuit device of claim 1, wherein the feedback driver includes an output driver that outputs the equalizing signal onto an external bus that includes the signal path.

15. A method of operation within an integrated circuit device, the method comprising:

capturing samples of a data signal from a signal path in response to a sampling clock signal;

outputting an equalizing signal onto the signal path in response to a first clock signal; and

adjusting a phase of the first clock signal to achieve phase alignment between transitions of the equalizing signal and transitions of the data signal.

16. The method of claim 15 further comprising generating the sample clock signal and, when a control signal is in a first state, adjusting a phase of the sampling clock signal to reduce a phase difference between the sampling clock signal and transitions in the data signal.

17. The method of claim 16 further comprising suspending adjustment of the phase of the sampling clock signal when the control signal is in a second state.

18. The method of claim 17 further comprising adjusting the phase of the first clock signal regardless of the state of the control signal such that, when the control signal is in the first state, a substantially fixed phase offset is maintained between the first clock signal and the sampling clock signal, and, when the control signal is in the second state, the phase offset between the first clock signal and the sampling clock signal is adjusted.

19. The method of claim 15 further comprising:

generating a predetermined sequence of values; and

selecting, as a source of equalizer tap values, from one of the predetermined sequence of values and data values that correspond to the samples of the data signal, and wherein outputting the equalizing signal onto the signal path comprises outputting an equalizing signal having a sequence of signal levels according to the source of equalizer tap values.

20. The method of claim 15 wherein the first clock signal is phase advanced relative to the sampling clock signal according to a propagation delay associated with at least a feedback driver.

21. A method of operation within an equalizing receiver, the method comprising:

outputting a test signal onto a signal path in response to transitions of a first clock signal;

sampling the test signal in response to transitions of a second clock signal; and

adjusting a phase of the first clock signal until transitions in the test signal have a predetermined phase relationship to the transitions of the second clock signal.

22. The method of claim 21 wherein outputting the test signal onto the signal path in response to transitions of the first clock signal comprises selecting a signal generator to source a sequence of values to an equalizing output driver, the equalizing output driver outputting the test signal according to the sequence of values.

23. The method of claim 22 wherein selecting the signal generator to source the sequence of values comprises selecting the signal generator in response to a control signal being in a first state.

24. The method of claim 21 wherein sampling the test signal in response to transitions of a second clock signal comprises:

receiving the test signal at an input of a sampling circuit coupled to the signal path; and

capturing samples of the test signal received at the input of the sampling circuit in response to transitions of the second clock signal.

25. The method of claim 21 wherein adjusting a phase of the first clock signal until transitions in the test signal have a predetermined phase relationship to the transitions of the first clock signal comprises adjusting a phase of the first clock signal until transitions in the test signal are phase aligned with transitions of a third clock signal, the transitions of the third clock signal having a substantially fixed phase relationship with transitions of the second clock signal.

26. The method of claim 25 wherein the transitions of the third clock signal have a quadrature phase relationship to the transitions of the second clock signal.

27. The method of claim 21 wherein outputting a test signal onto the signal path comprises outputting an alternating sequence of two distinct signal levels onto the signal path.