Encoding non-derministic finite automation states efficiently in a manner that permits simple and fast union operations

• US 8,862,585 B2
• Filed: 10/10/2012
• Issued: 10/14/2014
• Est. Priority Date: 10/10/2012
• Status: Active Grant

• Current Assignee: Polytechnic Institute Of New York University (New York University)
• Original Assignee: Polytechnic Institute Of New York University (New York University)
• Inventors: Chao, H. Jonathan, Xu, Yang
• Primary Examiner(s): Beausoliel, Jr., Robert
• Assistant Examiner(s): ALLEN, NICHOLAS E
• Application Number:
  US13/648,452
• Publication Number:
  US 20140101157A1
• Time in Patent Office: 734 Days
• Field of Search: None
• US Class Current: 707/737
• CPC Class Codes: H04L 43/028 by filtering
• CPC Class Codes: H04L 63/1416 Event detection, e.g. attack signature detection

Abstract

Deterministic Finite Automatons (DFAs) and Nondeterministic Finite Automatons (NFAs) are two typical automatons used in the Network Intrusion Detection System (NIDS). Although they both perform regular expression matching, they have quite different performance and memory usage properties. DFAs provide fast and deterministic matching performance but suffer from the well-known state explosion problem. NFAs are compact, but their matching performance is unpredictable and with no worst case guarantee. A new automaton representation of regular expressions, called Tunable Finite Automaton (TFA), is described. TFAs resolve the DFAs'"'"' state explosion problem and the NFAs'"'"' unpredictable performance problem. Different from a DFA, which has only one active state, a TFA allows multiple concurrent active states. Thus, the total number of states required by the TFA to track the matching status is much smaller than that required by the DFA. Different from an NFA, a TFA guarantees that the number of concurrent active states is bounded by a bound factor b that can be tuned during the construction of the TFA according to the needs of the application for speed and storage. A TFA can achieve significant reductions in the number of states and memory space.

Claims

1. A computer-implemented method for representing NFA states efficiently, in a way permits efficient union operations, the computer-implemented method comprising:

a) generating, with a computer system including at least one processor, an independent graph representing the NFA states as nodes and whether the NFA states can not be simultaneously active as edges;

b) dividing, with the computer system, the nodes of the graph into a small number of maximal cliques; and

c) encoding, with the computer system, each of the nodes using a number and size of the maximal cliques.

2. The computer-implemented method of claim 1 wherein the act of encoding each of the nodes includesnumbering the maximal cliques sequentially, starting at one,encoding nodes in the first maximal clique contiguously using bit position 1 to bit position ┌

log₂ (m₁+1)┐

, with other bit positions being set to “

0”

, wherein m₁ is the size of maximal clique₁, and

3) for each maximal clique following the first maximal clique, encoding the nodes in the j^th maximal clique continuously using bit position

3. The computer-implemented method of claim 1 wherein the act of encoding each of the nodes using the number and size of the maximal cliques encodes each state of the NFA as a bit vector.

4. Apparatus comprising:

a) at least one processor; and

b) at least one storage device storing processor executable instructions which, when executed by the at least one processor, cause the at least one processor to perform a method for representing NFA states efficiently, in a way permits efficient union operations, method including

1) generating an independent graph representing the NFA states as nodes and whether the NFA states can not be simultaneously active as edges;

2) dividing the nodes of the graph into a small number of maximal cliques; and

3) encoding each of the nodes using a number and size of the maximal cliques.

5. The apparatus of claim 4 wherein the act of encoding each of the nodes includes

A) numbering the maximal cliques sequentially, starting at one,

B) encoding nodes in the first maximal clique continguously using bit position 1 to bit position ┌

log₂ (m₁+1)┐

, with other bit positions being set to “

0”

, wherein m₁ is the size of maximal clique₁, and

C) for each maximal clique following the first maximal clique, encoding the nodes in the j^th maximal clique continuously using bit position

6. The apparatus of claim 4 wherein the act of encoding each of the nodes using the number and size of the maximal cliques encodes each state of the NFA as a bit vector.

7. A non-transitory machine readable storage medium storing processor executable instructions which, when executed by at least one processor, cause the at least one processor to perform a method for representing NFA states efficiently, in a way permits efficient union operations, the method including:

a) generating, with a computer system including at least one processor, an independent graph representing the NFA states as nodes and whether the NFA states can not be simultaneously active as edges;

b) dividing, with the computer system, the nodes of the graph into a small number of maximal cliques; and

c) encoding, with the computer system, each of the nodes using a number and size of the maximal cliques.

8. The non-transitory machine readable storage medium of claim 7 wherein the act of encoding each of the nodes includesnumbering the maximal cliques sequentially, starting at one,encoding nodes in the first maximal clique continguously using bit position 1 to bit position ┌

log₂ (m₁+1)┐

, with other bit positions being set to “

0”

, wherein m₁ is the size of maximal clique₁, and

3) for each maximal clique following the first maximal clique, encoding the nodes in the j^th maximal clique continuously using bit position

9. The non-transitory machine readable storage medium of claim 7 wherein the act of encoding each of the nodes using the number and size of the maximal cliques encodes each state of the NFA as a bit vector.