Architecture for address mapping of managed non-volatile memory

• US 8,862,851 B2
• Filed: 12/21/2012
• Issued: 10/14/2014
• Est. Priority Date: 12/23/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Toelkes, Tahoma, Wakrat, Nir Jacob, Corlett, Barry, Khmelnitsky, Vadim, Fai, Anthony, Post, Daniel Jeffrey, Thio, Hsiao, Herman, Kenneth L
• Primary Examiner(s): Bertram, Ryan
• Application Number:
  US13/725,671
• Publication Number:
  US 20130212318A1
• Time in Patent Office: 662 Days
• Field of Search: 711/154, 711/168
• US Class Current: 711/168
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Claims

1. A non-volatile memory (NVM) package, comprising:

an interface configured to receive a block address and a first chip enable signal from a host processor coupled to the interface;

a plurality of concurrently addressable memory units each containing a plurality of blocks; and

a processor configured to;

activate, in response to the first chip enable signal from the host processor, a first concurrently addressable memory unit using a first internal chip select enable signal;

activate a second concurrently addressable memory unit using a second internal chip select enable signal;

map the block address to blocks in the activated first and second concurrently addressable memory units;

execute a sequence of commands for concurrently performing read or write operations on the blocks in the activated first and second currently addressable memory units;

receive a command from the interface for an operation, wherein the operation includes a sequence of commands that perform atomic transactions on one or more of the concurrently addressable memory units; and

wherein a quantity of data that is read from or written to one of the one or more concurrently addressable memory units is equal to a product of N, a stride parameter for the concurrently addressable memory unit and a number of bytes equivalent to a page size plus a number of bytes associated with page allowing for metadata, where N is a positive integer representing a number of pages to be read or written, and stride is a number of blocks for operation commands within the concurrently addressable memory unit.

2. The package of claim 1, where the NVM package is a managed NAND package.

3. The package of claim 1, further comprising:

an error correction engine for applying error correction to a block of data read from, or written to the concurrently addressable memory units.

4. The package of claim 3, wherein the error detection and correction engine is included in one or more of the concurrently addressable memory units.

5. The package of claim 1, further comprising:

a pipeline management engine for managing throughput to the concurrently addressable memory units.

6. A system comprising:

a non-volatile memory (NVM) package; and

a host processor configured to provide a block address and a first chip enable signal to the NVM package, wherein the NVM package comprises a plurality of concurrently addressable memory units each containing a plurality of blocks and a processor configured to;

activate, in response to the first chip enable signal from the host processor, a first concurrently addressable memory unit using a first internal chip select enable signal,

activate a second concurrently addressable memory unit using a second internal chip select enable signal;

map the block address to blocks in the activated first and second concurrently addressable memory units;

execute a sequence of commands for concurrently performing read or write operations on the blocks in the activated first and second currently addressable memory units; and

receive a command from the interface for an operation, wherein the operation includes a sequence of commands that perform atomic transactions on one or more of the concurrently addressable memory units;

wherein a quantity of data that is read from or written to one of the one or more concurrently addressable memory units is equal to a product of N, a stride parameter for the concurrently addressable memory unit and a number of bytes equivalent to a page size plus a number of bytes associated with page allowing for metadata, where N is a positive integer representing a number of pages to be read or written, and stride is a number of blocks for operation commands within the concurrently addressable memory unit.

7. The system of claim 6, where the NVM package is a managed NAND package.

8. The system of claim 6, further comprising:

an error correction engine for applying error correction to a block of data read from, or written to the concurrently addressable memory units.

9. The system of claim 8, wherein the error detection and correction engine is included in one or more of the concurrently addressable memory units.

10. The system of claim 6, further comprising:

a pipeline management engine for managing throughput to the concurrently addressable memory units.

11. A method comprising:

receiving, by a processor of a non-volatile memory (NVM) package via an interface, a block address and a first chip enable signal from a host processor, wherein the NVM package includes a plurality of concurrently addressable memory units each containing a plurality of blocks;

activating, by the processor in response to the chip enable signal from the host processor, a first concurrently addressable memory unit of the NVM package using a first internal chip select enable signal;

activating, by the processor, a second concurrently addressable memory unit of the NVM package using a second internal chip select enable signal;

mapping the block address to blocks in the activated first and second concurrently addressable memory units;

executing a sequence of commands for concurrently performing read or write operations on the blocks in the activated first and second currently addressable memory units; and

receiving, by the processor, a command from the host processor for an operation, wherein the operation includes a sequence of commands that carry out concurrent atomic transactions on one or more of the concurrently addressable memory units;

wherein a quantity of data that is read from, or written to one of the one or more concurrently addressable memory units is equal to a product of N, a stride parameter for the concurrently addressable memory unit and a number of bytes equivalent to a page size plus a number of bytes associated with page allowing for metadata, where N is a positive integer representing a number of pages to be read or written, and stride is a number of blocks for operation commands within the concurrently addressable memory unit.

12. The method of claim 11, where the NVM package is a managed NAND package.

13. The method of claim 11, further comprising applying, by an error correction engine, error correction to a block of data read from or written to the concurrently addressable memory units.

14. The method of claim 11, wherein the error detection and correction engine is included in one or more of the concurrently addressable memory units.

15. The package of claim 14, further comprising managing, by a pipeline management engine, throughput to the concurrently addressable memory units.