Hardware controlled PLL switching

• US 8,862,926 B2
• Filed: 08/16/2011
• Issued: 10/14/2014
• Est. Priority Date: 08/16/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: de Cesare, Josh P., Cho, Jung Wook, Takayanagi, Toshinari
• Primary Examiner(s): WANG, ALBERT C
• Application Number:
  US13/211,004
• Publication Number:
  US 20130043917A1
• Time in Patent Office: 1,155 Days
• Field of Search: 713/500, 713/501
• US Class Current: 713/501
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation

Abstract

A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The hardware PLL switching (HPS) control block receives PLL switch requests from software. The request identifies a given core clock received by a given processing core of multiple processor cores on the SOC and indicates the identified core clock is not to be provided anymore by a current PLL. The request indicates a given search method including search conditions. The HPS control block searches for a target PLL that satisfies these search conditions. In response to finding the target PLL, the HPS control block changes clock network connections and parameters across the die of the SOC. These changes across the die disconnect the identified core clock from the current PLL and connects the identified core clock to the target PLL.

Claims

1. A method comprising:

providing via a clock switching network a plurality of core clocks;

receiving a software-initiated request specifying a phase lock loop (PLL) configuration for a first core clock of the plurality of core clocks;

searching via a hardware control block for a given PLL of a plurality of PLLs which satisfies the request; and

controlling the clock switching network to switch connection of the first core clock from a current PLL to the given PLL.

2. The method as recited in claim 1, further comprising the hardware control block identifying a subset of PLLs within the plurality of PLLs, wherein each PLL in the subset of PLLs is able to provide the first core clock.

3. The method as recited in claim 2, wherein in response to determining the request indicates an already enabled target PLL is preferred, the method further comprises the hardware control block searching any enabled PLLs within said subset that satisfy further conditions specified in the request.

4. The method as recited in claim 3, wherein in response to determining no enabled PLLs are in said subset and each enabled PLL does not have a same PLL setting as settings specified in the request, the method further comprises the hardware control block:

determining conditions indicated by the received request permit a disabled PLL to be enabled; and

in response to said determining;

selecting a disabled PLL in said subset as the target PLL;

loading the PLL settings specified in the request into the target PLL; and

enabling the target PLL.

5. The method as recited in claim 2, wherein in response to determining one or more enabled PLLs are in said subset and have a same PLL setting as settings specified in the request, the method further comprises a hardware control block selecting an unused PLL as the target PLL.

6. The method as recited in claim 5, wherein in response to determining one or more enabled PLLs are in said subset and each enabled PLL does not have a same PLL setting as settings specified in the request, the method further comprises the hardware control block:

determining conditions indicated by the received request permit settings to be loaded into a target PLL; and

in response to said determining;

selecting one of the enabled PLLs in said subset as the target PLL; and

loading the PLL settings specified in the request into the target PLL.

7. The method as recited in claim 2, wherein in response to not finding the target PLL, the method further comprises the hardware control block searching again according to different conditions specified in another search method indicated by the request.

8. The method as recited in claim 2, wherein in response to not finding the target PLL after searching for the target PLL according to each search method indicated in the request, the method further comprises the hardware control block sending an associated message to software.

9. A system-on-a-chip (SOC) comprising:

a plurality of phase lock loops (PLLs);

a clock switching network; and

a hardware PLL switching (HPS) control block coupled to the clock switching network, wherein the HPS control block is configured to;

receive a software-initiated request specifying a phase lock loop (PLL) configuration for a first core clock of the plurality of core clocks;

search for a given one of a plurality of PLLs as a target PLL, wherein the target PLL satisfies conditions specified in the PLL configuration; and

configure the clock switching network to switch connection of the first core clock from a current PLL to the target PLL.

10. The SOC as recited in claim 9, wherein the HPS control block is further configured to identify a plurality of PLLs that are able to provide the first core clock.

11. The SOC as recited in claim 10, wherein in response to determining the request identifies a method which prefers an already enabled target PLL, the HPS control block is further configured to first search for any enabled PLLs that satisfy the request.

12. The SOC as recited in claim 11, wherein in response to determining there are no unused PLLs in said subset, the HPS control block is configured to select an unused PLL as the target PLL.

13. The SOC as recited in claim 11, wherein in response to determining one or more enabled PLLs are in said subset, the HPS control block is further configured to:

select one of the enabled PLLs in said subset as the target PLL; and

load the PLL settings specified in the request into the target PLL.

14. The SOC as recited in claim 11, wherein in response to determining no enabled PLLs are in said subset, the HPS control block is further configured to:

select a disabled PLL in said subset as the target PLL;

load the PLL settings specified in the request into the target PLL; and

enable the target PLL.

15. The SOC as recited in claim 10, wherein in response to not finding the target PLL, the HPS control block is configured to search again according to method indicated by the request.

16. The SOC as recited in claim 15, wherein in response to not finding the target PLL after searching again for the target PLL, the HPS control block is further configured to send an associated message to software via the software interface.

17. An apparatus comprising:

a plurality of tables storing information corresponding to operating characteristics of a plurality of phase lock loops (PLLs); and

control logic coupled to each of a first interface, a second interface and the plurality of tables, wherein the control logic is configured to;

receive via the first interface a software-initiated request specifying a phase lock loop (PLL) configuration for a first core clock of the plurality of core clocks;

search for a given one of a plurality of PLLs on the SOC as a target PLL, wherein the target PLL satisfies conditions specified in the PLL configuration; and

in response to finding the target PLL, control the clock switching network to provide the first core clock via the target PLL.

18. The HPS control block as recited in claim 17, wherein the control logic is further configured to identify a plurality of PLLS PLLs operable to provide the first core clock.

19. The HPS control block as recited in claim 18, wherein the control logic is further configured to first search only currently enabled PLLs in response to detecting the request indicates an enabled PLL is preferred.

20. The HPS control block as recited in claim 19, wherein in response to determining an enabled PLL is not available, the HPS control block is further configured to select an unused PLL as the target PLL.

21. A clock source switching system comprising:

a clock switching network (CSN) configured to provide a plurality of core clocks, each of said core clocks being provided from one of a plurality of phase locked loops (PLLs);

a clock control circuit coupled to receive a software request that specifies a requested PLL configuration for one of a plurality of clock outputs, wherein the clock control circuit is configured to select one of the plurality of PLLs that matches the requested configuration and to control the CSN to connect the selected PLL to the one of the plurality of clock outputs;

wherein the control circuit is configured to perform a search of the PLLs according to one of a plurality of methods indicated by the request.

22. The clock source switching system as recited in claim 21, wherein said methods include:

static switching and dynamic switching.