Statistical distribution based variable-bit error correction coding
First Claim
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1. A method comprising:
- in a data storage device that includes a memory, wherein the memory has a three-dimensional (3D) memory configuration, performing;
providing user data to a variable-bit error correction coding (ECC) encoder that generates a first set of parity bits, wherein a first number of parity bits in the first set of parity bits is determined based on stored counts of read errors;
storing the user data, the first set of parity bits, and a second set of parity bits to the memory;
reading the user data and the first set of parity bits from the memory;
initiating a first decode operation using the user data and the first set of parity bits; and
in response to the first decode operation failing, accessing the second set of parity bits to initiate a second decode operation that uses the user data and the second set of parity bits.
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Abstract
A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.
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Citations
23 Claims
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1. A method comprising:
in a data storage device that includes a memory, wherein the memory has a three-dimensional (3D) memory configuration, performing; providing user data to a variable-bit error correction coding (ECC) encoder that generates a first set of parity bits, wherein a first number of parity bits in the first set of parity bits is determined based on stored counts of read errors; storing the user data, the first set of parity bits, and a second set of parity bits to the memory; reading the user data and the first set of parity bits from the memory; initiating a first decode operation using the user data and the first set of parity bits; and in response to the first decode operation failing, accessing the second set of parity bits to initiate a second decode operation that uses the user data and the second set of parity bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A data storage device comprising:
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a memory, wherein the memory has a three-dimensional (3D) memory configuration; and a controller coupled to the memory, wherein the controller is configured to provide user data to a variable-bit error correction coding (ECC) encoder to generate a first set of parity bits, wherein the controller is further configured to store the user data, the first set of parity bits, and a second set of parity bits to the memory, wherein a first number of parity bits in the first set of parity bits is determined based on stored counts of read errors, and wherein the controller is further configured to read the user data and the first set of parity bits from the memory, to initiate a first decode operation using the user data and the first set of parity bits, and to access, in response to the first decode operation failing, the second set of parity bits to initiate a second decode operation that uses the user data and the second set of parity bits. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification