Method and system for error management in a memory device

• US 8,862,973 B2
• Filed: 12/09/2009
• Issued: 10/14/2014
• Est. Priority Date: 12/09/2009
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Intel Corporation
• Inventors: Bains, Kuljit S., Zimmerman, David J., Brzezinski, Dennis W., Williams, Michael, Halbert, John B.
• Primary Examiner(s): MCCARTHY, CHRISTOPHER S
• Application Number:
  US12/634,286
• Publication Number:
  US 20110138261A1
• Time in Patent Office: 1,770 Days
• Field of Search: None
• US Class Current: 714/800
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error

Abstract

A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

Claims

1. A method comprising:

receiving by a memory device, a command and a parity bit signal associated with the command;

detecting whether the received command has a parity error; and

receiving by the memory device one or more subsequent commands during a first interval after the received command; and

responsive to a detection of the parity error of the received command,

ignoring the received command;

storing command bits and address bits of the received command;

ignoring the one or more subsequent commands received in the first interval;

asserting an error indication signal;

asserting an error status bit;

waiting until all of one or more current commands has finished execution,

wherein the one or more current commands are received prior to the received command;

waiting until an active-to-precharge command delay has lapsed; and

closing all open pages.

2. The method of claim 1, wherein detecting whether the received command has the parity error comprises:

determining whether the command bits or the address bits of the received command has the parity error.

3. The method of claim 1, wherein responsive to the detection of the parity error and during a second interval subsequent to the first interval, the method further comprising:

responding only to one of a refresh command, a mode register set (MRS) read command or a MRS write command.

4. The method of claim 3, wherein responsive to the detection of the parity error, the method further comprising:

determining that the error status bit is de-asserted;

de-asserting the indication signal.

5. The method of claim 1, further comprising:

detecting whether a write operation has a cyclic redundancy check (CRC) error; and

responsive to a detection of the CRC error, sending a pulse on the indication signal.

6. A method comprising:

detecting whether a parity error or a cyclic redundancy check (CRC) error is indicated on an indication signal; and

responsive to a detection of the parity error, waiting until all of one or more sent commands has completed execution;

sending a pre-charge command and a refresh command to all of one or more memory modules; and

determining which one of the one or more memory modules has received a command with the parity error.

7. The method of claim 6, wherein detecting whether the parity error or the CRC error is indicated on the indication signal comprises:

determining whether an asserted signal or a pulse is sent on the indication signal.

8. The method of claim 6, wherein determining which one of the one or more memory modules has received the command with the parity error comprises:

reading an error status bit of each of the one of more memory modules to determine which one of the one or more memory modules has received the command with the parity error, wherein the error status bit is to indicate the parity error.

9. The method of claim 8, wherein responsive to a detection of the parity error, the method further comprising:

resetting the error status bit of the determined one memory module; and

sending the command to the determined one memory module.

10. The method of claim 6, further comprising:

responsive to a detection of the CRC error, determining which one of the one or more memory modules has performed a write operation with the CRC error; and

performing the write operation to the determined one memory module that has performed the write operation with the CRC error.

11. The method of claim 10, wherein determining which one of the one or more memory modules has performed the write operation with the CRC error comprises:

determining which one of the one or more memory modules has performed a write operation with the CRC error based on a delay time of the indication signal.

12. A device, the device comprising a memory module, the memory module comprising:

a register; and

error handling logic to;

receive a command, and a parity bit signal associated with the command, and one or more subsequent commands during a first interval after the received command;

detect whether the received command has a parity error; and

responsive to a detection of the parity error of the received command,

ignore the received command;

store command bits and address bits of the received command in the register;

ignore the one or more subsequent commands received in the first interval;

assert an error indication signal;

assert an error status bit of the register;

wait until all of one or more current commands have finished execution, wherein the one or more current commands are received prior to the received command;

wait until an active-to-precharge command delay has lapsed; and

close all open pages.

13. The device of claim 12, wherein the error handling logic to detect whether the received command has the parity error is to:

determine whether the command bits or the address bits of the received command has the parity error.

14. The device of claim 12, wherein the error handling logic responsive to the detection of the parity error and during a second interval subsequent to the first interval, is further to:

respond only to one of a refresh command, a mode register set (MRS) read command or a MRS write command.

15. The device of claim 12, wherein the error handling logic responsive to the detection of the parity error is further to:

determine that the error status bit is de-asserted;

de-assert the indication signal.

16. The device of claim 12, wherein the error handling logic is further to:

detect whether a write operation has a cyclic redundancy check (CRC) error; and

responsive to a detection of the CRC error, send a pulse on the indication signal.

17. The device of claim 12, wherein the memory module is a double-data-rate four synchronous dynamic random access memory (DDR4 SDRAM).

18. The device of claim 12 further comprising a memory controller, the memory controller comprising:

logic to perform tasks, to;

provide a command and a parity bit signal associated with the command to a plurality of memory modules;

detect whether an indication of a parity error of the command is received; and

responsive to a detection of the indication of the parity error, determine which one of the plurality of memory modules has received the command,

wherein the logic comprises at least one of hardware adapted to perform the tasks,

and a combination of hardware and software adapted to perform the tasks, said combination of hardware and software including machine readable instructions stored on the hardware of the combination that when executed, causes the machine to perform the tasks.

19. The device of claim 18, wherein the logic to provide the parity bit signal associated with the command is to:

compute parity of address signals and command signals of the command; and

select a bit signal as the provided parity bit signal associated with the command, wherein the bit signal is selected based on an even or odd parity of a combination of the computed parity and the bit signal.

20. The device of claim 18, wherein the logic responsive to the detection of the indication of the parity error is further to:

wait until all of one or more sent commands to the plurality of one or more memory modules have completed execution; and

send a pre-charge command and a refresh command to all memory modules.

21. The device of claim 18, wherein the logic to determine which one of the plurality of memory modules has received the command is to:

reading an error status bit of each of the plurality of memory modules to determine which one of the plurality of memory modules has received the command, wherein the error status bit is to indicate the parity error.

22. The device of claim 21, wherein the logic responsive to the detection of the indication of the parity error is further to:

reset the error status bit of the determined one memory module; and

send the command to the determined one memory module.

23. The device of claim 18, wherein the logic is further to:

detect whether another indication of a cyclic redundancy check (CRC) error of the command is received; and

responsive to a detection of the another indication of the CRC error,

determine which one of the plurality of memory modules has received the command; and

send the command to the determined one memory module.

24. A memory controller comprising:

logic to perform tasks, to;

detect whether a parity error or a cyclic redundancy check (CRC) error is indicated on an indication signal; and

responsive to a detection of the parity error, wait until all of one or more sent commands has completed execution;

send a pre-charge command and a refresh command to all of one or more memory devices; and

determine which one of the one or more memory devices has received a command with the parity error.

25. The memory controller of claim 24, wherein the logic to detect whether the parity error or the CRC error is indicated on the indication signal is to:

determine whether an asserted signal or a pulse is sent on the indication signal.

26. The memory controller of claim 24, wherein the logic to determine which one of the one or more memory devices has received the command with the parity error is to:

read an error status bit of each of the one or more memory devices to determine which one of the one or more memory devices has received the command with the parity error, wherein the error status bit is to indicate the parity error.

27. The memory controller of claim 24, wherein responsive to a detection of the parity error, the logic is to:

reset the error status bit of the determined one memory device; and

send the command to the determined one memory device.

28. The memory controller of claim 24, further comprising:

responsive to a detection of the CRC error, the logic is to determine which one of the one or more memory devices has performed a write operation with the CRC error; and

to perform the write operation to the determined one memory device that has performed the write operation with the CRC error.

29. The memory controller of claim 24, wherein the logic to determining which one of the one or more memory modules has performed the write operation with the CRC error is to:

determine which one of the one or more memory modules has performed a write operation with the CRC error based on a delay time of the indication signal.