SRAM cell layout structure and devices therefrom

• US 8,863,064 B1
• Filed: 02/26/2013
• Issued: 10/14/2014
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Kidd, David A., Clark, Lawrence T., Tien, George
• Primary Examiner(s): Whitmore, Stacy
• Assistant Examiner(s): DIMYAN, MAGID Y
• Application Number:
  US13/776,917
• Time in Patent Office: 595 Days
• Field of Search: 716/100, 716/119
• US Class Current: 716/119
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A method for modifying a design of an integrated circuit includes obtaining design layout data for the integrated circuit and selecting at least one SRAM cell in the integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer. The method also includes extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout. The method further includes adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the SRAM cell and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.

Claims

1. A computer-implemented method for designing an integrated circuit, comprising:

obtaining design layout data for a base integrated circuit with at least one SRAM cell to be converted to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer; and

performing, via a processor, the steps of;

dividing NMOS active area patterns in the design layout into at least one enhanced body effect (EBE) NMOS active area layout with the NMOS active area patterns for the at least one SRAM cell and at least one non-EBE NMOS active layout with other ones of the NMOS active area patterns;

dividing PMOS active area patterns in the design layout into at least one EBE PMOS active area layout with the PMOS active area patterns for the at least one SRAM cell and at least one non-EBE PMOS active layout with other ones of the PMOS active area patterns;

adjusting a size of the NMOS active area patterns in the EBE NMOS active area layout to reduce a width of at least pull-down devices in the at least one SRAM cell; and

altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.

2. The method of claim 1, further comprising:

after the altering and adjusting, selecting process parameters such that electrical parameters for transistors in the at least one SRAM cell meet a criteria, the selection of the process parameters based at least on the EBE NMOS active area layout, the EBE PMOS active area layout, and the gate layer layout.

3. The method of claim 1, wherein the step of adjusting comprises resizing a portion of the EBE NMOS active area layout associated with the pull-down devices so that a width of the pull-down devices and a width of pass-gate devices in the at least one SRAM cell are substantially equal, wherein the step of altering comprises resizing the gate layer layout for the pull-up devices.

4. The method of claim 1, wherein the step of adjusting comprises resizing a portion of the EBE NMOS active area layout associated with the pull-down devices so that a width of the pull-down devices and a width of pass-gate devices in the at least one SRAM cell are substantially equal, wherein the step of altering comprises resizing the gate layer layout for the pull-up devices, and wherein the step of adjusting further comprises reducing a width of the EBE NMOS active areas so that at least one overall dimension of the at least one SRAM cell is reduced.

5. The method of claim 1, wherein the step of altering comprises resizing the gate layer layout for the pull-down devices, and wherein the step of adjust comprises reducing widths of the pull-down devices and pass-gate devices in the at least one SRAM cell so that one overall dimension of the at least one SRAM cell is reduced.

6. The method of claim 1, wherein the step of adjusting comprises resizing a portion of the EBE NMOS active area layout associated with the pull-down devices so that a width of the pull-down devices and a width of pass-gate devices in the at least one SRAM cell are substantially equal, wherein the step of altering comprises resizing the gate layer layout for the pull-down devices.