LED having a low defect N-type layer that has grown on a silicon substrate

• US 8,865,565 B2
• Filed: 08/02/2011
• Issued: 10/21/2014
• Est. Priority Date: 08/02/2011
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Chen, Zhen
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Naraghi, Ali
• Application Number:
  US13/196,854
• Publication Number:
  US 20130032834A1
• Time in Patent Office: 1,176 Days
• Field of Search: 257 90-100, 257/88, 257/E21.09, 438455-459
• US Class Current: 438/458
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A vertical GaN-based blue LED has an n-type GaN layer that was grown directly on Low Resistance Layer (LRL) that in turn was grown over a silicon substrate. In one example, the LRL is a low sheet resistance GaN/AlGaN superlattice having periods that are less than 300 nm thick. Growing the n-type GaN layer on the superlattice reduces lattice defect density in the n-type layer. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form finished LED devices. In some examples, some or all of the LRL remains in the completed LED device such that the LRL also serves a current spreading function. In other examples, the LRL is entirely removed so that no portion of the LRL is present in the completed LED device.

Claims

1. A method of manufacturing a Light Emitting Diode (LED) device, comprising:

(a) forming a buffer layer on a silicon substrate, and then forming a template layer on the buffer layer;

(b) forming a superlattice structure directly on the template layer, wherein the superlattice structure includes a plurality of periods, and wherein each period of the superlattice structure includes an aluminum-gallium-nitride sublayer and a gallium-nitride sublayer;

(c) forming an n-type layer over and directly on the superlattice structure;

(d) forming an active layer over the n-type layer, wherein the active layer includes an amount of indium;

(e) forming a p-type layer over the active layer such that the silicon substrate, the buffer layer, the template layer, the superlattice structure, the n-type layer, the active layer, and the p-type layer form a first structure;

(f) bonding a conductive carrier to the first structure thereby forming a second structure;

(g) removing the silicon substrate from the second structure thereby forming a third structure.

2. The method of manufacturing of claim 1, further comprising:

(h) forming electrodes on the third structure; and

(i) singulating the third structure thereby forming the LED device.

3. The method of manufacturing of claim 2, wherein the superlattice structure is entirely removed along with the silicon substrate in (g).

4. The method of manufacturing of claim 2, wherein some but not all of the superlattice structure is removed along with the silicon substrate in (g).

5. The method of manufacturing of claim 2, wherein the superlattice structure and a part of the n-type layer are removed along with the silicon substrate in (g).

6. The method of manufacturing of claim 1, wherein the n-type layer comprises a plurality of periods, wherein each period of the n-type layer includes a gallium-nitride sublayer and an aluminum-gallium-nitride, wherein gallium-nitride sublayers of the n-type layer are thicker than the gallium-nitride sublayers of the superlattice structure, and wherein the aluminum-gallium-nitride sublayers of the n-type layer are thinner than the aluminum-gallium-nitride sublayers of the superlattice structure.

7. The method of manufacturing of claim 1, wherein the aluminum-gallium-nitride sublayers of the superlattice structure have a silicon concentration less than 1×

10¹⁸ atoms/cm³, and wherein the aluminum-gallium-nitride sublayers of the n-type layer have a silicon concentration greater than 1×

10¹⁸ atoms/cm³.

8. The method of manufacturing of claim 1, wherein the superlattice structure meets the n-type layer at an interface, wherein the superlattice structure has a sheet resistance at the interface, wherein the n-type layer has a sheet resistance at the interface, and wherein the sheet resistance of the superlattice structure at the interface is smaller than the sheet resistance of the n-type layer at the interface.

9. The method of manufacturing of claim 1, wherein the n-type layer comprises a plurality of periods, wherein each period of the n-type layer includes a relatively thick sublayer of gallium-nitride and a relatively thin layer of another material, and wherein the other material is taken from the group consisting of:

aluminum nitride, and silicon doped aluminum-gallium-nitride.

10. The method of manufacturing of claim 1, further comprising:

after (g) roughening a surface of the superlattice structure.

11. The method of claim 1, wherein the bonding of (f) comprises using a eutectic bond metal layer to wafer bond a carrier wafer structure to the first structure, wherein the conductive carrier is a part of the carrier wafer structure.

12. A Light Emitting Diode (LED) device for emitting non-monochromatic light, the LED device comprising:

a Low Resistance Layer (LRL) that includes a plurality of periods, wherein at least one of the periods of the LRL includes an aluminum-gallium-nitride sublayer and a gallium-nitride sublayer;

an n-type layer disposed in direct contact with the LRL;

a p-type layer;

an active layer disposed between the n-type layer and the p-type layer, wherein the active layer includes an amount of indium;

a conductive carrier;

a first electrode; and

a second electrode adapted to conduct a current, wherein the current flows from the second electrode, through the conductive carrier, through the p-type layer, through the active layer, through the n-type layer, through the LRL, and to the first electrode thereby causing the non-monochromatic light to be emitted.

13. The LED device of claim 12, wherein the n-type layer comprises a plurality of periods, wherein each period of the n-type layer includes a gallium-nitride sublayer and an aluminum-gallium-nitride, wherein gallium-nitride sublayers of the n-type layer are thicker than the gallium-nitride sublayers of the LRL, and wherein the aluminum-gallium-nitride sublayers of the n-type layer are thinner than the aluminum-gallium-nitride sublayers of the LRL.

14. The LED device of claim 13, wherein the aluminum-gallium-nitride sublayers of the LRL have a silicon concentration less than 1×

10¹⁸ atoms/cm³, and wherein the aluminum-gallium-nitride sublayers of the n-type layer have a silicon concentration greater than 1×

10¹⁸ atoms/cm³.

15. The LED device of claim 14, wherein the LRL has a sheet resistance, wherein the n-type layer has a sheet resistance, and wherein the sheet resistance of the LRL is smaller than the sheet resistance of the n-type layer.

16. The LED device of claim 12, wherein the LRL has a roughened surface, and wherein the first electrode is in direct contact with the LRL.

17. The LED device of claim 12, further comprising:

a eutectic bond metal layer disposed between the conductive carrier and the p-type layer.

18. A method of manufacturing, comprising:

(a) bonding a conductive carrier to a first structure thereby forming a second structure, wherein the first structure comprises;

a silicon substrate;

a superlattice structure disposed on the silicon substrate, wherein the superlattice structure includes a plurality of periods, wherein each period is less than three hundred nanometers thick and includes a sublayer of gallium nitride;

an n-type gallium-nitride layer disposed directly on the superlattice structure;

a p-type gallium-nitride layer; and

an active layer disposed between the n-type gallium-nitride layer and the p-type gallium-nitride layer, wherein the active layer comprises an amount of indium;

(b) removing the silicon substrate and some but not all of the superlattice structure from the second structure thereby forming a third structure that includes a part of the superlattice structure; and

(c) forming metal electrodes on the third structure.

19. A method of manufacturing, comprising:

(a) bonding a conductive carrier to a first structure thereby forming a second structure, wherein the first structure comprises;

a silicon substrate;

a superlattice structure disposed on the silicon substrate, wherein the superlattice structure includes a plurality of periods, wherein each period is less than three hundred nanometers thick and includes a sublayer of gallium nitride;

an n-type gallium-nitride layer disposed directly on the superlattice structure;

a p-type gallium-nitride layer; and

an active layer disposed between the n-type gallium-nitride layer and the p-type gallium-nitride layer, wherein the active layer comprises an amount of indium

(b) removing the silicon substrate, all of the superlattice structure, and some but not all of the n-type gallium-nitride layer from the second structure thereby forming a third structure that includes a part of the n-type layer; and

(c) forming metal electrodes on the third structure.