Transistor, method of manufacturing the transistor and electronic device including the transistor

• US 8,866,136 B2
• Filed: 07/28/2010
• Issued: 10/21/2014
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Ji-sim, Lee, Chang-seung, Lee, Jae-cheol, Lee, Sang-yoon, Kwon, Jang-yeon, Lee, Kwang-hee, Son, Kyoung-seok
• Primary Examiner(s): Sefer, A.
• Application Number:
  US12/805,379
• Publication Number:
  US 20110127518A1
• Time in Patent Office: 1,546 Days
• Field of Search: 257/43, 257/59, 257/72, 438/38, 438/104
• US Class Current: 257/43
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided are a transistor, a method of manufacturing the transistor, and an electronic device including the transistor. The transistor may include a passivation layer on a channel layer, a source, a drain, and a gate, wherein the component of the passivation layer is varied in a height direction. The passivation layer may have a multi-layer structure including a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer sequentially stacked. The channel layer may include an oxide semiconductor.

Claims

1. A transistor comprising:

a channel layer including an oxide;

a source electrode and a drain electrode configured to separately contact both ends of the channel layer, the source electrode covering a first region of the channel layer and the drain electrode covering a second region of the channel layer;

a gate corresponding to the channel layer;

a gate insulating layer between the channel layer and the gate, the gate insulating layer including a silicon nitride layer and a silicon oxide layer which are sequentially stacked from the gate; and

a passivation layer on the channel layer, the source and drain electrodes, the gate insulating layer, and the gate, the passivation layer including a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer sequentially stacked,

wherein the silicon oxynitride layer includes oxygen through an entire thickness,

wherein a portion of the channel layer between the first region and the second region, which is not covered by the source electrode and the drain electrode, is a plasma-treated region that is treated with plasma including oxygen, and the portion of the channel layer includes oxygen provided by the plasma, and

wherein the portion of the channel layer between the first region and the second region has an oxygen concentration that is different from the oxygen concentration of a portion of the channel layer that is covered by the source electrode and the drain electrode.

2. The transistor of claim 1, wherein the channel layer includes a ZnO-based oxide.

3. The transistor of claim 2, wherein the ZnO-based oxide further includes indium (In).

4. The transistor of claim 3, wherein the ZnO-based oxide further includes at least one of the group consisting of hafnium (Hf), yttrium (Y), tantalum (Ta), zirconium (Zr), titanium (Ti), copper (Cu), nickel (Ni), gallium (Ga), aluminum (Al), tin (Sn), and magnesium (Mg).

5. The transistor of claim 4, wherein the ZnO-based oxide includes hafnium indium zinc oxide (HfInZnO).

6. The transistor of claim 1, wherein the silicon oxynitride layer has a thickness of about 100 nm to about 400 nm.

7. The transistor of claim 1, wherein the channel layer is on the gate.

8. The transistor of claim 7, further comprising:

an etch stop layer on the channel layer, wherein the source electrode and the drain electrode are on both ends of the etch stop layer.

9. The transistor of claim 1, wherein the gate is on the channel layer.

10. A flat display device comprising the transistor of claim 1.

11. A method of manufacturing a transistor, the method comprising:

preparing a transistor including a channel layer, a source electrode and a drain electrode separately contacting both ends of the channel layer, a gate corresponding to the channel layer, and a gate insulating layer between the channel layer and the gate, the channel layer including an oxide and the gate insulating layer including a silicon nitride material layer and a silicon oxide material layer sequentially stacked from the gate, the source electrode covering a first region of the channel layer and the drain electrode covering a second region of the channel layer; and

forming a passivation layer on the channel layer,

wherein forming the passivation layer includes,

forming a silicon oxide layer on the transistor,

forming a silicon oxynitride layer on the silicon oxide layer, wherein the silicon oxynitride layer includes oxygen through an entire thickness, and

forming a silicon nitride layer on the silicon oxynitride layer, and

wherein a portion of the channel layer between the first region and the second region, which is not covered by the source electrode and the drain electrode, is a plasma-treated region treated with plasma including oxygen, and the portion of the channel layer includes oxygen provided by the plasma, and

wherein the portion of the channel layer between the first region and the second region has an oxygen concentration that is different from the oxygen concentration of a portion of the channel layer that is covered by the source electrode and the drain electrode.

12. The method of claim 11, wherein at least one of the silicon oxide layer, the silicon oxynitride layer, and the silicon nitride layer is formed using plasma-enhanced chemical vapor deposition (PECVD).

13. The method of claim 11, wherein a first reaction gas including ammonia (NH₃) as a source gas of nitrogen (N) is used for forming the silicon oxynitride layer, and a second reaction gas including NH₃ as the source gas of N is used for forming the silicon nitride layer, and

wherein a flow rate of NH₃ of the first reaction gas is lower than a flow rate of NH₃ of the second reaction gas.

14. The method of claim 11, wherein the silicon oxynitride layer is formed at a lower pressure than the silicon nitride layer.

15. The method of claim 11, wherein the silicon oxynitride layer is formed using a lower source power than the silicon nitride layer.

16. The method of claim 11, wherein the silicon oxynitride layer is formed to have a thickness of about 100 nm to about 400 nm.

17. The method of claim 11, wherein the channel layer includes a ZnO-based oxide.

18. The method of claim 17, wherein the ZnO-based oxide further includes indium (In).

19. The method of claim 18, wherein the ZnO-based oxide further includes at least one of the group consisting of Hf, Y, Ta, Zr, Ti, Cu, Ni, Ga, Al, Sn, and Mg.

20. The method of claim 19, wherein the ZnO-based oxide includes hafnium indium zinc oxide (HfInZnO).

21. The method of claim 11, wherein the transistor has at least one of a bottom gate structure and a top gate structure.

22. The method of claim 21, wherein the transistor has a bottom gate structure, further comprising:

forming an etch stop layer on the channel layer, wherein the source electrode and the drain electrode are on both ends of the etch stop layer.

23. The method of claim 11, wherein prior to forming the passivation layer, further comprising:

treating an exposed portion of the channel layer with plasma including oxygen.

24. A method of manufacturing a flat display device comprising the method of manufacturing a transistor according to claim 11.

25. A transistor comprising:

a channel layer including an oxide;

an etch stop layer on the channel layer;

a source electrode and a drain electrode configured to separately contact both ends of the channel layer;

a gate corresponding to the channel layer;

a gate insulating layer between the channel layer and the gate, the gate insulating layer including a silicon nitride layer and a silicon oxide layer which are sequentially stacked from the gate; and

a passivation layer covering the channel layer, the source and drain electrodes, the gate insulating layer, and the gate, the passivation layer including a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer sequentially stacked,

wherein the silicon oxynitride layer includes oxygen through an entire thickness,

wherein the channel layer is above the gate, the source electrode and the drain electrode are on both ends of the etch stop layer, the source electrode covers an upper surface of a first end of the etch stop layer, and the drain electrode covers an upper surface of a second end of the etch stop layer,

wherein a portion of the channel layer between the first region and the second region, which is not covered by the source electrode and the drain electrode, is a plasma-treated region that is treated with plasma including oxygen, and the portion of the channel layer includes oxygen provided by the plasma, and

wherein the portion of the channel layer between the first region and the second region has an oxygen concentration that is different from the oxygen concentration of a portion of the channel layer that is covered by the source electrode and the drain electrode.