High-voltage transistor device with integrated resistor

• US 8,866,201 B2
• Filed: 02/10/2012
• Issued: 10/21/2014
• Est. Priority Date: 12/05/2007
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Banerjee, Sujit, Parthasarathy, Vijay
• Primary Examiner(s): Tran, Tony
• Application Number:
  US13/385,264
• Publication Number:
  US 20120146105A1
• Time in Patent Office: 984 Days
• Field of Search: 257/272, 257/E27.016
• US Class Current: 257/272
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1058 with PN junction gate
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Claims

1. A power integrated circuit (IC) device comprising:

a substrate of a first conductivity type;

a well region of a second conductivity type disposed in the substrate, the well region having first, second, and third areas, the first area being laterally adjacent to the second area, and the second area being laterally adjacent to the third area, the second area laterally and physically separating the first area from the third area;

a JFET disposed in the first area of the well region, the JFET including;

first and second regions of the second conductivity type; and

one or more first buried regions of the first conductivity type, the one or more first buried regions defining a plurality of conduction channels that extend substantially across the first area, the first region being disposed at one end and the second region being disposed at an opposite end, of the conduction channels;

a dielectric layer formed over at least the second area of the well region, the second area extending vertically from the dielectric layer to a bottom of the well region, the second area being devoid of any buried region of the second conductivity type;

a layer of material formed as a resistor over the dielectric layer directly above the second area, the resistor having first and second ends;

first and second electrodes, the first electrode being electrically and physically connected to the first end, and the second electrode being electrically and physically connected to the second end, of the resistor, the second electrode also being electrically connected to the second region;

a third electrode electrically connected to the first region;

a fourth electrode electrically connected to the substrate and to the one or more first buried regions, wherein a voltage provided at the third electrode is substantially proportional to a voltage difference between the second and fourth electrodes when the voltage difference is less than a pinch-off voltage of the JFET, the voltage provided at the third electrode being substantially constant when the voltage difference is greater than the pinch-off voltage of the JFET.

2. The power IC device of claim 1 further comprising a plurality of vertically spaced-apart second buried regions of the first conductivity type disposed in the third area of the well region.

3. The power IC device of claim 2 wherein the one or more second buried regions are electrically connected to the fourth electrode.

4. The power IC device of claim 1 wherein the dielectric layer comprises a field oxide layer.

5. The power IC device of claim 1 wherein the layer of resistive material comprises a polysilicon resistor.

6. The power IC device of claim 1 wherein when the first electrode is at a high voltage greater than 100 volts and the fourth electrode is at or near a ground potential, the second area is at a voltage substantially the same as the high voltage.

7. The power IC device of claim 1 wherein the layer of resistive material floats at a potential substantially equal to the voltage difference when the voltage difference is greater than the pinch-off voltage of the JFET.

8. The power IC device of claim 1 wherein the one or more first buried regions comprise a plurality of buried regions, the conduction channels being defined between each of the first buried regions, and also between a bottommost one of the first buried regions and the substrate.

9. The power IC device of claim 1 wherein the one or more first buried regions comprise a single first buried region of the first conductivity type with the conduction channels being defined above and below the single first buried region.

10. The power IC device of claim 1 wherein the one or more first buried regions are separated from both the first and second regions.