Vertical gate LDMOS device

• US 8,866,217 B2
• Filed: 08/10/2012
• Issued: 10/21/2014
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor LLC (Analog Devices, Inc.)
• Inventors: Zuniga, Marco A., Lu, Yang, Fatemizadeh, Badredin, Prasad, Jayasimha, Paul, Amit, Ruan, Jun
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US13/572,015
• Publication Number:
  US 20130105887A1
• Time in Patent Office: 802 Days
• Field of Search: 257/330, 257/335, 257/343, 257/E29.257, 257/E29.258
• US Class Current: 257/330
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.

Claims

1. A transistor comprising:

an n-well region implanted into a surface of a substrate;

a trench in then-well region, the trench having a first side and an opposing second side, the trench extending from the surface to a first depth, the trench comprising

a gate of conductive material in the trench, and

dielectric material filling a volume of the trench not filled by the conductive material;

a p-type material in a first region extending from a second depth to a third depth in then-well region, wherein each of the second depth and the third depth is greater than the first depth;

a source region on the first side of the trench, the source region including a p-body region wherein an n+ region and a p+ region is implanted in the p-body region; and

a drain region on the second side of the trench, the drain region comprising an n+ region.

2. The transistor of claim 1 wherein a distance of the gate from the first side of the trench is less than a distance of the gate from the second side of the trench.

3. The transistor of claim 1 wherein a breakdown voltage of the transistor is substantially between a range 10V-100V.

4. The transistor of claim 1 wherein the conductive material is polysilicon.

5. The transistor of claim 1 wherein the dielectric material is an oxide.

6. The transistor of claim 1, wherein the first region is below the trench and a width of the first region is more than a width of the trench.

7. The transistor of claim 1, wherein the first region and the source region define a channel through which a current flows around the trench from the source region to the drain region.

8. The transistor of claim 1, wherein a concentration of the p-type material in the first region is lower than a concentration of the p-type material in the p-body region.

9. The transistor of claim 8, wherein the p-body region includes a deep p-body region and a shallow p-body region, the shallow p-body region being closer to the surface and having a higher concentration of the p-type material than the deep p-body region.

10. The transistor of claim 1, wherein the p-body region extends from the surface to the first region.

11. The transistor of claim 1 comprising a gate electrode in electrical contact with the gate of conductive material in the trench.

12. The transistor of claim 11 comprising a layer of silicide between the gate electrode and the gate of conductive material in the trench.

13. A transistor comprising:

an n-well region implanted into a surface of a substrate;

a trench in then-well region, the trench having a first side and an opposing second side, the trench extending from the surface to a first depth, the trench comprising

a gate of conductive material in the trench, and

dielectric material filling a volume of the trench not filled by the conductive material;

a source region on the first side of the trench, the source region including a p-body region wherein an n+ region and a p+ region is implanted in the p-body region;

a drain region on the second side of the trench, the drain region comprising an n+ region, the n+ region abutting the trench, and

a p-type material in a first region extending from a second depth to a third depth in the n-well region, wherein each of the second depth and the third depth is greater than the first depth.

14. A transistor comprising:

an n-well region implanted into a surface of a substrate;

a trench in then-well region, the trench having a first side and an opposing second side, the trench extending from the surface to a first depth, the trench comprising

a first dielectric material abutting the n-well on the first side and the opposing second side of the trench,

a source side dielectric liner on the first dielectric material on a source side of the trench,

a drain side dielectric liner on the first dielectric material on a drain side of the trench,

a gate of conductive material filling a first volume in the trench between the source side dielectric liner and the source side dielectric liner and abutting the source side dielectric liner, and

wherein the first dielectric material fills a second volume of the trench between the source side dielectric liner and the source side dielectric liner not filled by the conductive material;

a source region on the first side of the trench, the source region including a p-body region wherein an n+ region and a p+ region is implanted in the p-body region; and

a drain region on the second side of the trench, the drain region comprising an n+ region.

15. The transistor of claim 14, wherein the source-side dielectric liner and the drain side dielectric liner comprise silicon nitride.

16. The transistor of claim 14, wherein the first dielectric material comprises silicon oxide.