Super junction semiconductor device comprising a cell area and an edge area

• US 8,866,221 B2
• Filed: 07/02/2012
• Issued: 10/21/2014
• Est. Priority Date: 07/02/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Weber, Hans, Schulze, Hans-Joachim, Wahl, Uwe
• Primary Examiner(s): SHINGLETON, MICHAEL B
• Application Number:
  US13/539,973
• Publication Number:
  US 20140001552A1
• Time in Patent Office: 841 Days
• Field of Search: 257/339, 257/492, 257/493, 257/133, 257/E27.055
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

A drift layer of a super junction semiconductor device includes first portions of a first conductivity type and second portions of a second conductivity type opposite to the first conductivity type. The first and second portions are formed both in a cell area and in an edge area surrounding the cell area, wherein an on-state or forward current through the drift layer flows through the first portions in the cell area. At least one of the first and second portions other than the first portions in the cell area includes an auxiliary structure or contains auxiliary impurities to locally reduce the avalanche rate. Locally reducing the avalanche rate increases the total voltage blocking capability of the super junction semiconductor device.

Claims

1. A super junction semiconductor device comprising:

at least one doped zone in a cell area;

a drift layer formed in the cell area and in an edge area surrounding the cell area, the drift layer comprising first portions of the first conductivity type and second portions of a second conductivity type opposite to the first conductivity type, an on-state or forward current from/to the at least one doped zone flowing through the first portions in the cell area; and

wherein at least one of the first and second portions other than the first portions in the cell area contain auxiliary impurities or include an auxiliary structure operable to locally reduce an avalanche rate.

2. The super junction semiconductor device of claim 1, wherein the auxiliary impurities are operable to locally reduce a charge carrier mean free path.

3. The super junction semiconductor device of claim 1, wherein the auxiliary impurities are operable to locally reduce an electric field strength.

4. The super junction semiconductor device of claim 1, wherein the auxiliary structure is operable to locally reduce an electric field strength.

5. The super junction semiconductor device of claim 1, wherein the auxiliary impurities are operable to increase scattering of charge carriers in the drift layer.

6. The super junction semiconductor device of claim 1, wherein the auxiliary impurities substitute atoms of a semiconductor material forming the drift layer in a crystal lattice of the semiconductor material and are suitable to scatter charge carriers by the perturbation of a crystal potential of the crystal lattice.

7. The super junction semiconductor device of claim 1, wherein the auxiliary impurities are effective as donors or acceptors and at least partially compensate for a doping of the second portions by impurities of the second conductivity type.

8. The super junction semiconductor device of claim 1, wherein the auxiliary impurities are effective as donors and acceptors and compensate for each other.

9. The super junction semiconductor device of claim 1, wherein at least one of the second portions in the edge area contains the auxiliary impurities or includes the auxiliary structure.

10. The super junction semiconductor device of claim 1, wherein all second portions in the cell and edge areas contain the auxiliary impurities or includes the auxiliary structures.

11. The super junction semiconductor device of claim 1, wherein at least one of the first portions in the edge area contains the auxiliary impurities.

12. The super junction semiconductor device of claim 1, wherein all of the first and second portions in the edge area contain the auxiliary impurities.

13. The super junction semiconductor device of claim 1, wherein the first and second portions are stripe-shaped and are arranged in alternating order along a direction perpendicular to a flow direction of the on-state or forward current.

14. The super junction semiconductor device of claim 1, wherein the auxiliary structures are provided from a charged dielectric material.

15. The super junction semiconductor device of claim 1, wherein each auxiliary structure has a mean dielectric permittivity deviating from that of a semiconductor material of the drift layer by not more than 20%.

16. The super junction semiconductor device of claim 1, wherein each auxiliary structure comprises at least two sub-layers of different materials.

17. The super junction semiconductor device of claim 1, wherein each auxiliary structure is arranged in a central portion of one of the second portions.

18. The super junction semiconductor device of claim 1, wherein the auxiliary impurities and the auxiliary structure are absent in the first portions in the cell area.

19. A super junction diode comprising the super junction semiconductor device of claim 1, wherein the at least one doped zone is of the second conductivity type and directly adjoins the first and second portions in the cell area.

20. A super junction insulated gate field effect transistor comprising the super junction semiconductor device of claim 1, wherein each of the doped zones is of the first conductivity type and directly adjoins a base zone of the second conductivity type, each base zone directly adjoining at least one the first and to one of the second portions.

21. A method of manufacturing a super junction semiconductor device, the method comprising:

forming a drift layer, the drift layer comprising, in a cell area and in an edge area surrounding the cell area, first portions of the first conductivity type and second portions of a second conductivity type opposite to the first conductivity type;

forming at least one doped zone above the drift layer in the cell area, wherein an on-state current or forward current from/to the at least one doped zone flows through the first portions in the cell area; and

providing in at least one of the first and second portions other than the first portions in the cell area auxiliary impurities or an auxiliary structure operable to locally reduce an avalanche rate.

22. The method of claim 21, wherein the drift layer is formed by iterating a process sequence comprising growing a sub-layer by epitaxy and implanting dopants into the sub-layer.

23. The method of claim 22, wherein at least one of the iterated process sequences comprises providing the auxiliary impurities by an auxiliary implant process.

24. The method of claim 23, wherein the auxiliary implant process comprises a masked implant using an implant mask shielding the cell area and not-shielding at least a part of the edge area.

25. The method of claim 23, wherein the grown sub-layer is intrinsic, sections of the first portions are implanted using a first implant mask shielding the second portions, and sections of the second portions are implanted using a second implant mask shielding the first portions.

26. The method of claim 25, wherein the one of the first and second masked implants with the lower implant dose uses a mask not shielding the edge area and the one of the first and second masked implants with the higher implant dose uses a mask with wider openings in the edge area than in the cell area.