Charge compensation semiconductor device

• US 8,866,222 B2
• Filed: 02/28/2013
• Issued: 10/21/2014
• Est. Priority Date: 03/07/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weber, Hans, Gamerith, Stefan, Hirler, Franz
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Hillman, Damian A
• Application Number:
  US13/780,753
• Publication Number:
  US 20130234761A1
• Time in Patent Office: 600 Days
• Field of Search: 257/340, 257/341, 257/335, 257/337, 257/322, 257/490, 257/495, 257/E29.27, 257/E29.066, 257/E29.256, 257/E29.416, 257/E29.418
• US Class Current: 257/340
• CPC Class Codes: H01L 21/02365 Forming inorganic semiconducting materials on a substrate for light-sensitive devices H01L31/00
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state

Abstract

A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Claims

1. A circuit for driving a load, comprising:

a designed circuit voltage; and

at least one semiconductor switch having a rated break-down voltage higher than the designed circuit voltage, the at least one semiconductor switch comprising;

a semiconductor body having a first surface and comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type adjoining the first semiconductor layer, a third semiconductor layer of the first conductivity type adjoining the second semiconductor layer, and a body region of a second conductivity type forming a pn-junction with the first semiconductor layer;

a source metallization arranged on the first surface and in ohmic contact with the body region; and

a drain metallization in ohmic contact with the third semiconductor layer,

wherein the first semiconductor layer comprises a compensation-structure in ohmic contact with the source metallization and the third semiconductor layer comprises a floating compensation-structure.

2. The circuit of claim 1, wherein the floating compensation-structure is only depleted when a reverse voltage applied between the drain metallization and the source metallization exceeds the designed circuit voltage.

3. The circuit of claim 1, wherein the first semiconductor layer comprises, in a vertical cross-section substantially orthogonal to the first surface, at least two compensation regions of a second conductivity type, each of the at least two compensation regions being in ohmic contact with the source metallization and forming a pn-junction with a first portion of the first semiconductor layer, the first portion of the first semiconductor layer being arranged between the at least two compensation regions and forming a pn-compensation-structure with the at least two compensation regions.

4. The circuit of claim 1, wherein the second semiconductor layer is comprised of a semiconductor material having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material.

5. The circuit of claim 1, wherein the circuit comprises a half-bridge, and wherein at least one of a high-side switch and a low-side switch of the half-bridge is formed by the at least one semiconductor switch.

6. The circuit of claim 5, wherein the half-bridge comprises a controller which is adapted to control at least one of the high-side switch and the low-side switch such that the respective pn-junction is forwardly biased at least several times during driving the load.

7. The circuit of claim 1, wherein the circuit comprises a resonant tank formed as an LLC circuit comprising a capacitor and two inductors, and wherein one of the source metallization and the drain metallization is connected to the capacitor.

8. The circuit of claim 1, wherein the at least one semiconductor switch is a power MOSFET.

9. The circuit of claim 1, wherein the semiconductor body further comprises a fourth semiconductor layer of the first conductivity type adjoining the third semiconductor layer and having a maximum doping concentration which is higher than a maximum doping concentration of the third semiconductor layer.