Semiconductor device with staggered oxide-filled trenches at edge region

• US 8,866,255 B2
• Filed: 12/17/2009
• Issued: 10/21/2014
• Est. Priority Date: 03/12/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Schulze, Hans-Joachim, Voss, Stephan, Zundel, Markus
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): HALL, VICTORIA KATHLEEN
• Application Number:
  US12/640,532
• Publication Number:
  US 20100155879A1
• Time in Patent Office: 1,769 Days
• Field of Search: 257/339, 257/341, 257/342, 257/487, 257/488, 257/491, 257/506, 257/510, 257513-515, 257/622, 257/626, 257/509, 257/127, 257/170, 257/409, 257/484, 257/605, 257/725, 257/730, 257/773, 438/140, 438/106, 438/110, 438/113, 438/778, 438/787
• US Class Current: 257/513
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device is provided that comprises a semiconductor substrate comprising an active area and a peripheral region adjacent the active area and structure positioned in the peripheral region for hindering the diffusion of mobile ions from the peripheral region into the active area.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first major surface;

an active area;

an edge region surrounding the active area; and

two or more discontinuous trenches positioned in the edge region and arranged at intervals and at least substantially surrounding the active area, each of the two or more discontinuous trenches including a plurality of discrete trench portions separated by gaps, the plurality of discrete trench portions arranged in a single row;

wherein the discrete trench portions of one row are arranged directly in front of the gaps between the discrete trench portions of an adjacent row; and

wherein the discrete trench portions of each of the two or more discontinuous trenches are filled with one or more oxides and covered by a dielectric layer positioned directly on the first major surface such that the dielectric layer contacts the first major surface.

2. The semiconductor device of claim 1, wherein

the two or more discontinuous trenches are positioned in an area of a junction termination of the semiconductor device.

3. The semiconductor device of claim 2, wherein

the two or more discontinuous trenches are positioned between the junction termination and outermost source areas.

4. The semiconductor device of claim 1, wherein

the two or more discontinuous trenches of adjacent rows are offset with respect to one another.

5. The semiconductor device of claim 1, wherein

in plan view, the discrete trench portions of one row are generally rectangular trenches, and the discrete trench portions of another row are U-shaped trenches.

6. The semiconductor device of claim 1, wherein the semiconductor device is a vertical MOSFET device.

7. The semiconductor device of claim 1, wherein the semiconductor device is an insulated gate bipolar transistor (IGBT).