Surface charge reduction technique for capacitive sensors
First Claim
1. A differential capacitive transducer system that senses a physical quantity, the differential capacitive transducer system comprising:
- a first capacitive core generating a first core output based on the physical quantity, the first capacitive core including a first variable capacitor, a second variable capacitor, a first core input coupled to the first variable capacitor, a second core input coupled to the second variable capacitor, and a first core output coupled to a first common node between the first variable capacitor and the second variable capacitor;
a second capacitive core generating a second core output based on the physical quantity, the second capacitive core including a third variable capacitor, a fourth variable capacitor, a third core input coupled to the third variable capacitor, a fourth core input coupled to the fourth variable capacitor, and a second core output coupled to a second common node between the third variable capacitor and the fourth variable capacitor;
a chopping system having a high state and a low state, the chopping system being coupled to the first and second capacitive cores, the chopping system having a first chopping input coupled to a first positive signal, a second chopping input coupled to a second negative signal, a third chopping input coupled to a first negative signal, a fourth chopping input coupled to a second positive signal, a first chopping output and a second chopping output,wherein when the chopping system is in the high state, the first chopping input is coupled to the first core input to supply the first positive signal to the first variable capacitor, the second chopping input is coupled to the second core input to supply the second negative signal to the second variable capacitor, the third chopping input is coupled to the third core input to supply the first negative signal to the third variable capacitor, the fourth chopping input is coupled to the fourth core input to supply the second positive signal to the fourth variable capacitor, the first chopping output is coupled to the first core output and the second chopping output is coupled to the second core output; and
wherein when the chopping system is in the low state, the first chopping input is coupled to the third core input to supply the first positive signal to the third variable capacitor, the second chopping input is coupled to the fourth core input to supply the second negative signal to the fourth variable capacitor, the third chopping input is coupled to the first core input to supply the first negative signal to the first variable capacitor, the fourth chopping input is coupled to the second core input to supply the second positive signal to the second variable capacitor, the first chopping output is coupled to the second core output and the second chopping output is coupled to the first core output.
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Abstract
A differential capacitive transducer system is disclosed that includes first and second capacitive cores and a chopping system. The first core a first input coupled to a first capacitor, a second input coupled to a second capacitor, and a first output. The second core includes a third input coupled to a third capacitor, a fourth input coupled to a fourth capacitor, and a second output. The chopping system has first and fourth inputs coupled to positive signals, and second and third inputs coupled to negative signals. As the chopping system switches between high and low states, it couples the core inputs to different polarity signals reducing charge buildup. The different polarity signals can have substantially same magnitudes. Chopper clock and main clock frequencies can be selected to provide substantially zero average voltages at the core inputs. The system can include an integrator circuit and differential summing circuits.
5 Citations
20 Claims
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1. A differential capacitive transducer system that senses a physical quantity, the differential capacitive transducer system comprising:
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a first capacitive core generating a first core output based on the physical quantity, the first capacitive core including a first variable capacitor, a second variable capacitor, a first core input coupled to the first variable capacitor, a second core input coupled to the second variable capacitor, and a first core output coupled to a first common node between the first variable capacitor and the second variable capacitor; a second capacitive core generating a second core output based on the physical quantity, the second capacitive core including a third variable capacitor, a fourth variable capacitor, a third core input coupled to the third variable capacitor, a fourth core input coupled to the fourth variable capacitor, and a second core output coupled to a second common node between the third variable capacitor and the fourth variable capacitor; a chopping system having a high state and a low state, the chopping system being coupled to the first and second capacitive cores, the chopping system having a first chopping input coupled to a first positive signal, a second chopping input coupled to a second negative signal, a third chopping input coupled to a first negative signal, a fourth chopping input coupled to a second positive signal, a first chopping output and a second chopping output, wherein when the chopping system is in the high state, the first chopping input is coupled to the first core input to supply the first positive signal to the first variable capacitor, the second chopping input is coupled to the second core input to supply the second negative signal to the second variable capacitor, the third chopping input is coupled to the third core input to supply the first negative signal to the third variable capacitor, the fourth chopping input is coupled to the fourth core input to supply the second positive signal to the fourth variable capacitor, the first chopping output is coupled to the first core output and the second chopping output is coupled to the second core output; and wherein when the chopping system is in the low state, the first chopping input is coupled to the third core input to supply the first positive signal to the third variable capacitor, the second chopping input is coupled to the fourth core input to supply the second negative signal to the fourth variable capacitor, the third chopping input is coupled to the first core input to supply the first negative signal to the first variable capacitor, the fourth chopping input is coupled to the second core input to supply the second positive signal to the second variable capacitor, the first chopping output is coupled to the second core output and the second chopping output is coupled to the first core output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A capacitive transducer system that senses a physical quantity, the differential capacitive transducer system comprising:
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a first capacitive core generating a first core output, the first capacitive core including a first variable capacitor, a second variable capacitor, a first core input coupled to the first variable capacitor, a second core input coupled to the second variable capacitor, and a first core output coupled to a first common node between the first variable capacitor and the second variable capacitor; a second capacitive core generating a second core output, the second capacitive core including a third variable capacitor, a fourth variable capacitor, a third core input coupled to the third variable capacitor, a fourth core input coupled to the fourth variable capacitor, and a second core output coupled to a second common node between the third variable capacitor and the fourth variable capacitor; a chopping system oscillating between a high state and a low state coupled to the first and second capacitive cores, wherein when the chopping system is in the low state, a first high input of the first and second core inputs receives a positive voltage and a first low input of the first and second core inputs receives a negative voltage, the first high input and the first low input being different inputs; and
a second high input of the third and fourth core inputs receives a positive voltage and a second low input of the third and fourth core inputs receives a negative voltage, the second high input and the second low input being different inputs; andwherein when the chopping system is in the high state, the first high input receives a negative voltage and the first low input receives a positive voltage, the second high input receives a negative voltage and the second low input receives a positive voltage. - View Dependent Claims (13, 14)
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15. A differential capacitive transducer system that senses a physical quantity, the differential capacitive transducer system comprising:
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a first capacitive core generating a first core output based on the physical quantity, the first capacitive core including a first variable capacitor, a second variable capacitor, a first core input coupled to the first variable capacitor, a second core input coupled to the second variable capacitor, and a first core output coupled to a first common node between the first variable capacitor and the second variable capacitor; a second capacitive core generating a second core output based on the physical quantity, the second capacitive core including a third variable capacitor, a fourth variable capacitor, a third core input coupled to the third variable capacitor, a fourth core input coupled to the fourth variable capacitor, and a second core output coupled to a second common node between the third variable capacitor and the fourth variable capacitor; a chopping system having a high state and a low state, the chopping system being coupled to the first and second capacitive cores, the chopping system having a first chopping input coupled to a first positive signal, a second chopping input coupled to a second negative signal, a third chopping input coupled to a first negative signal, a fourth chopping input coupled to a second positive signal, a first chopping output and a second chopping output, output circuitry receiving the first and second core outputs and generating a transducer signal; a main clock having a main clock frequency, the main clock controlling the charging and discharging of the first and second capacitor cores; a chopping clock having a chopping clock frequency, the chopping clock controlling when the chopping system is in the high state and the low state; wherein when the chopping system is in the high state, the first chopping input is coupled to the first core input to supply the first positive signal to the first variable capacitor, the second chopping input is coupled to the second core input to supply the second negative signal to the second variable capacitor, the third chopping input is coupled to the third core input to supply the first negative signal to the third variable capacitor, the fourth chopping input is coupled to the fourth core input to supply the second positive signal to the fourth variable capacitor, the first chopping output is coupled to the first core output and the second chopping output is coupled to the second core output; and wherein when the chopping system is in the low state, the first chopping input is coupled to the third core input to supply the first positive signal to the third variable capacitor, the second chopping input is coupled to the fourth core input to supply the second negative signal to the fourth variable capacitor, the third chopping input is coupled to the first core input to supply the first negative signal to the first variable capacitor, the fourth chopping input is coupled to the second core input to supply the second positive signal to the second variable capacitor, the first chopping output is coupled to the second core output and the second chopping output is coupled to the first core output. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification