Information processing apparatus, control method therefor, and computer-readable storage medium

• US 8,867,086 B2
• Filed: 11/26/2013
• Issued: 10/21/2014
• Est. Priority Date: 12/07/2012
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Mima, Tsuyoshi
• Primary Examiner(s): Cato, Miya J
• Application Number:
  US14/090,384
• Publication Number:
  US 20140160531A1
• Time in Patent Office: 329 Days
• Field of Search: None
• US Class Current: 358/1.16
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: H04N 1/00965 using a plug-in memory module, e.g. memory card, memory stick
• CPC Class Codes: H04N 1/00978 Temperature control
• CPC Class Codes: H04N 1/32358 using picture signal storage, e.g. at transmitter H04N1/17 takes precedence
• CPC Class Codes: H04N 2201/0094 Multifunctional device, i.e. a device capable of all of reading, reproducing, copying, facsimile transception, file transception
• CPC Class Codes: H04N 2201/3297 Simultaneous use of a single memory for different image storage purposes
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

There is provided a mechanism of preferentially using a memory layer which suffers a small influence of heat of an SOC die, based on the positional relationship between the SOC die and the memory layer, and decreasing the refresh frequency of the DRAM and a leakage current. To accomplish this, an information processing apparatus allocates, in order to execute an accepted job, a memory area for executing the job preferentially from a memory physically farthest from the SOC die among a plurality of memories, and then executes the job.

Claims

1. An information processing apparatus including an SOC die having a CPU and a WideIO memory device in which a plurality of memories are stacked on said SOC die, comprising:

an acceptance unit configured to accept a job;

a memory control unit configured to allocate, in order to execute the job accepted by said acceptance unit, a memory area for executing the job preferentially from a memory physically farthest from said SOC die among the plurality of memories; and

an execution unit configured to execute the job using the memory area allocated by said memory control unit.

2. The apparatus according to claim 1, wherein

if it is impossible to allocate, from one memory, a memory area necessary for executing the job, said memory control unit allocates the memory area from a plurality of memories.

3. An information processing apparatus including an SOC die having a CPU and a WideIO memory device in which a plurality of memories are stacked on said SOC die, comprising:

an acceptance unit configured to accept a job;

a determination unit configured to determine whether or not the job accepted by said acceptance unit is a job which frequently accesses an allocated memory area during execution;

a memory control unit configured to allocate, if said determination unit determines that the job is a job which frequently accesses a memory area, a memory area for executing the job preferentially from a memory physically farthest from said SOC die among the plurality of memories, and allocate, if said determination unit determines that the job is not a job which frequently accesses a memory area, a memory area for executing the job preferentially from a memory physically closest to said SOC die among the plurality of memories; and

an execution unit configured to execute the job using the memory area allocated by said memory control unit.

4. The apparatus according to claim 3, further comprising

a table that stores a flag indicating, for each job, whether or not the job accepted by said acceptance unit is a job which frequently accesses an allocated memory area during execution,

wherein said determination unit refers to the flag to determine whether the job is a job which frequently accesses an allocated memory area.

5. The apparatus according to claim 3, wherein said execution unit simultaneously executes a plurality of jobs.

6. A control method for an information processing apparatus including an SOC die having a CPU and a WideIO memory device in which a plurality of memories are stacked on said SOC die, comprising:

causing an acceptance unit to accept a job;

causing a memory control unit to allocate, in order to execute the job accepted in the causing the acceptance unit to accept, a memory area for executing the job preferentially from a memory physically farthest from said SOC die among the plurality of memories; and

causing an execution unit to execute the job using the memory area allocated in the causing the memory control unit to allocate.

7. A non-transitory computer-readable storage medium storing a computer program for causing a computer to execute each step of a control method for an information processing apparatus according to claim 6.

8. A control method for an information processing apparatus including an SOC die having a CPU and a WideIO memory device in which a plurality of memories are stacked on said SOC die, comprising:

causing an acceptance unit to accept a job;

causing a determination unit to determine whether the job accepted in the causing the acceptance unit to accept is a job which frequently accesses an allocated memory area during execution;

causing a memory control unit to allocate, if it is determined in the causing the determination unit to determine that the job is a job which frequently accesses a memory area, a memory area for executing the job preferentially from a memory physically farthest from said SOC die among the plurality of memories, and to allocate, if it is determined in the causing the determination unit to determine that the job is not a job which frequently accesses a memory area, a memory area for executing the job preferentially from a memory physically closest to said SOC die among the plurality of memories; and

causing an execution unit to execute the job using the memory area allocated in the causing the memory control unit to allocate.

9. A non-transitory computer-readable storage medium storing a computer program for causing a computer to execute each step of a control method for an information processing apparatus according to claim 8.