Signal-powered integrated circuit with ESD protection

• US 8,867,182 B2
• Filed: 06/07/2010
• Issued: 10/21/2014
• Est. Priority Date: 06/23/2005
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Bark, Boris A., Grande, Brad L., Kiss, Peter, Ransijn, Johannes G., Yoder, James D.
• Primary Examiner(s): Fureman, Jared
• Application Number:
  US12/794,845
• Publication Number:
  US 20100246695A1
• Time in Patent Office: 1,597 Days
• Field of Search: 361/56, 361/91.1, 361/119, 379/93.06, 379/93.36, 379/102.04
• US Class Current: 361/56
• CPC Class Codes: H04M 19/001 Current supply source at the exchanger providing current to substations

Abstract

The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal'"'"'s predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.

Claims

1. A signal-powered integrated circuit, comprising:

an integrated circuit die including a ground node, a supply node configured to provide a supply voltage to a plurality of circuits on the integrated circuit die, and a first terminal for receiving an input signal having data content and a predetermined energy;

a receive buffer formed on the integrated circuit die, connected to the first terminal and capable of receiving the data content associated with the input signal, the receive buffer having an output terminal configured to output the buffered input signal;

a rectifier formed on the integrated circuit die, the rectifier including

a first diode connected between the first terminal and the ground node, and

a second diode connected between the first terminal and the supply node;

a transmit buffer having an input terminal and an output terminal that is connected to the first terminal of the integrated circuit die; and

a feedback path connected between the output terminal of the receive buffer and the input terminal of the transmit buffer, and configured such that the buffered input signal passes through the feedback path to the input terminal of the transmit buffer;

wherein;

the rectifier is capable of rectifying the input signal and passing at least a portion of the input signal'"'"'s predetermined energy to the supply node, and

each of the first and second diodes is capable of withstanding an ESD impulse.

2. The circuit of claim 1, wherein each diode in the rectifier is capable of withstanding an ESD impulse of at least about 1000 volts.

3. The circuit of claim 1, wherein each diode in the rectifier is capable of withstanding an ESD impulse in the range from about 1000 volts to about 2000 volts.

4. The circuit of claim 1, wherein the first and second diodes are parasitic diodes in a first transistor and a second transistor, respectively.

5. The signal-powered integrated circuit of claim 4, wherein the first and second transistors are complementary transistors in the transmit buffer.

6. The circuit of claim 1, wherein the average energy of the input signal is sufficiently large to cause the first and second diodes to operate as a rectifier.

7. The circuit of claim 1, wherein the first and second diodes are the primary devices or the only devices that protect the integrated circuit die from electrostatic discharge through the first terminal.

8. The circuit of claim 1, wherein:

the input signal is a differential input signal formed by a first signal and a second signal complementary to the first, and the first terminal is capable of receiving the first signal;

the integrated circuit die further includes a second terminal capable of receiving the second signal;

the rectifier further includes

a third diode connected between the second terminal and the ground node, and

a fourth diode connected between the second terminal and the supply node;

the first, second, third and fourth diodes together provide full-wave rectification for the differential input signal; and

each of the third and fourth diodes is capable of withstanding an ESD impulse.

9. The signal-powered integrated circuit of claim 1, wherein the supply node is connected to the receive buffer to provide the supply voltage to the receive buffer.

10. The signal-powered integrated circuit of claim 1, wherein the receive buffer is an amplifying-type buffer that amplifies the input signal.

11. The signal-powered integrated circuit of claim 1, wherein the feedback path comprises:

a mode-selection switch that is (i) configured to receive (a) the buffered input signal and (b) a reverse transmit signal for transmission via the first terminal, and (ii) configured to select either the buffered input signal or the reverse transmit signal and to pass the selected signal to the transmit buffer'"'"'s input terminal.

12. The signal-powered integrated circuit of claim 11, wherein the mode-selection switch is a multiplexer.

13. A method of powering an integrated circuit, comprising the steps of:

receiving a first input signal having data content and a predetermined energy at a first terminal of the integrated circuit;

passing a first portion of the first input signal through a first receive buffer to produce a first buffered input signal;

passing the first buffered input signal through a first feedback path to an input terminal of a first transmit buffer having a first output terminal connected to the first terminal of the integrated circuit;

rectifying a second portion of the first input signal via a first diode connected between the first terminal and a ground node of the integrated circuit, and a second diode connected between the first terminal and a supply node configured to provide a supply voltage to a plurality of circuits on the integrated circuit; and

storing at least a portion of the first input signal'"'"'s predetermined energy at the supply node;

wherein each of the first and second diodes is capable of withstanding an ESD impulse.

14. The method of claim 13, wherein each diode in the rectifier is capable of withstanding an ESD impulse of at least about 1000 volts.

15. The method of claim 13, wherein each diode in the rectifier is capable of withstanding an ESD impulse in the range from about 1000 volts to about 2000 volts.

16. The method of claim 13, wherein the first and second diodes are parasitic diodes in a first transistor and a second transistor, respectively.

17. The method of claim 13, wherein the first input signal has an average energy that is sufficiently large to enable the rectifier to rectify the input signal.

18. The method of claim 13, further comprising the step of protecting the integrated circuit from electrostatic discharge through the first terminal only by the first and second diodes.

19. The method of claim 13, further comprising the steps of:

receiving a second input signal having data content and a predetermined energy at a second terminal of the integrated circuit, the second input signal forming a differential input signal with the first input signal;

passing a first portion of the second input signal through a second receive buffer to produce a second buffered input signal;

passing the second buffered input signal through a second feedback path to an input terminal of a second transmit buffer having an output terminal connected to the second terminal of the integrated circuit;

rectifying a second portion of the second input signal via a third diode connected between the second terminal and the ground node of the integrated circuit, and a fourth diode connected between the second terminal and the supply node of the integrated circuit, each diode being capable of withstanding an ESD impulse; and

storing at least a portion of the second input signal'"'"'s predetermined energy at the supply node; and

thereby full-wave rectifying the differential input signal.

20. The method of claim 13, further comprising providing the supply voltage to the first receive buffer from the supply node.

21. The method of claim 16, wherein the first and second transistors are complementary transistors in the first transmit buffer.

22. The method of claim 13, wherein passing the first buffered input signal through the first feedback path to the input terminal of the first transmit buffer comprises:

a mode-selection switch receiving (a) the first buffered input signal and (b) a reverse transmit signal for transmission via the first terminal, selecting either the first buffered input signal or the reverse transmit signal, and passing the selected signal to the first transmit buffer'"'"'s input terminal.

23. The method of claim 22, wherein the mode-selection switch is a multiplexer.