Memory cell that includes multiple non-volatile memories

• US 8,867,258 B2
• Filed: 10/16/2012
• Issued: 10/21/2014
• Est. Priority Date: 03/22/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Rao, Hari M., Kim, Jung Pill, Haghighi, Siamack
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US13/653,079
• Publication Number:
  US 20130039119A1
• Time in Patent Office: 735 Days
• Field of Search: 365/148, 365/158, 365/154, 365/188, 365/189.08, 365/189.03, 365/189.04
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device includes a plurality of memory cells. At least one of the memory cells includes a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element. Each of the first non-volatile memory and the second non-volatile memory is accessible via multiple ports.

Claims

1. A memory device comprising:

a plurality of memory cells, wherein at least one of the memory cells comprises;

a first non-volatile memory including a first resistive memory element; and

a second non-volatile memory including a second resistive memory element, wherein each of the first non-volatile memory and the second non-volatile memory is accessible via multiple ports.

2. The memory device of claim 1, wherein a read operation is performed with respect to the first resistive memory element and a write operation is performed with respect to the second resistive memory element, and wherein the read operation and the write operation are performed concurrently.

3. The memory device of claim 1, wherein a read operation is performed with respect to the first resistive memory element and a write operation is performed with respect to the first resistive memory element, and wherein the read operation and the write operation are performed concurrently.

4. The memory device of claim 1, wherein a first read operation is performed with respect to the first resistive memory element and a second read operation is performed with respect to the second resistive memory element, and wherein the first read operation and the second read operation are performed concurrently.

5. The memory device of claim 1, wherein a first read operation is performed with respect to the first resistive memory element and a second read operation is performed with respect to the first resistive memory element, and wherein the first read operation and the second read operation are performed concurrently.

6. The memory device of claim 1, wherein a first write operation is performed with respect to the first resistive memory element and a second write operation is performed with respect to the second resistive memory element, and wherein the first write operation and the second write operation are performed concurrently.

37. The memory device of claim 1, wherein multiple bit lines and multiple sense lines couple the first non-volatile memory to the second non-volatile memory, and wherein at least one of the multiple bit lines and the multiple sense lines is usable in both read and write operations of the first non-volatile memory and the second non-volatile memory.

7. A system comprising:

a processor; and

a plurality of memory cells accessible to the processor, wherein at least one of the memory cells comprises;

a first non-volatile memory including a first resistive memory element; and

a second non-volatile memory including a second resistive memory element, wherein each of the first non-volatile memory and the second non-volatile memory is accessible via multiple ports.

8. The system of claim 7, further comprising a port-data selector coupled to each of the multiple ports, wherein the port-data-selector comprises:

a bit line multiplexer configured to select a bit line voltage to be applied to a bit line of a particular port of the multiple ports; and

a sense line multiplexer configured to select a sense line voltage to be applied to a sense line of the particular port of the multiple ports.

9. The system of claim 8, wherein the bit line voltage is selected from a first plurality of voltages including a first voltage, a second voltage, and a third voltage, and wherein the sense line voltage is selected from a second plurality of voltages including the first voltage and the second voltage.

10. The system of claim 9, wherein the first voltage is associated with zero volts, the second voltage is associated with a write voltage, and the third voltage is associated with a read voltage,

11. The system of claim 9, wherein a first selection of the bit line voltage and the sense line voltage enables a read operation, wherein a second selection of the bit line voltage and the sense line voltage enables a first write operation associated with writing a logical one value, and wherein a third selection of the bit line voltage and the sense line voltage enables a second write operation associated with writing a logical zero value.

12. The system of claim 11, wherein a fourth selection of the bit line voltage and the sense line voltage prohibits current flow between the bit line and the sense line.

13. The system of claim 12, wherein the fourth selection includes the bit line voltage and the sense line voltage equal to zero volts.

38. The system of claim 7, wherein multiple bit lines and multiple sense lines couple the first non-volatile memory to the second non-volatile memory, and wherein at least one of the multiple bit lines and the multiple sense lines is usable in both read and write operations of the first non-volatile memory and the second non-volatile memory.

14. A method comprising:

receiving first data and receiving second data at a single memory cell that comprises a first non-volatile memory and a second non-volatile memory;

storing the first data at a first resistive memory element of the first non-volatile memory; and

storing the second data at a second resistive memory element of the second non-volatile memory, wherein each of the first non-volatile memory and the second non-volatile memory is accessible via multiple ports.

15. The method of claim 14, wherein storing the first data is associated with a first write operation, wherein storing the second data is associated with a second write operation, and wherein the first write operation and the second write operation are performed concurrently.

16. The method of claim 14, further comprising:

performing a read operation with respect to the first resistive memory element; and

performing a write operation with respect to the second resistive memory element, wherein the read operation and the write operation are performed concurrently.

17. The method of claim 14, further comprising:

performing a read operation with respect to the first resistive memory element; and

performing a write operation with respect to the first resistive memory element, wherein the read operation and the write operation are performed concurrently.

18. The method of claim 14, further comprising:

performing a first read operation with respect to the first resistive memory element; and

performing a second read operation with respect to the second resistive memory element, wherein the first read operation and the second read operation are performed concurrently.

19. The method of claim 14, further comprising:

performing a first read operation with respect to the first resistive memory element; and

performing a second read operation with respect to the first resistive memory element, wherein the first read operation and the second read operation are performed concurrently.

20. The method of claim 14, further comprising:

selecting one or more bit line voltages associated with a bit line of a particular port of the multiple ports; and

selecting one or more sense line voltages associated with a sense line of the particular port of the multiple ports.

21. The method of claim 20, further comprising:

performing a read operation when a first of the one or more bit line voltages and a first of the one or more sense line voltages are selected;

performing a first write operation when a second of the one or more bit line voltages and a second of the one or more sense line voltages are selected; and

performing a second write operation when a third of the one or more bit line voltages and a third of the one or more sense line voltages are selected.

22. The method of claim 21, wherein, when a selected voltage of the one or more bit line voltages and a selected voltage of the one or more sense line voltages are at a same potential, read operations or write operations via the particular port are prohibited.

39. The method of claim 14, wherein multiple bit lines and multiple sense lines couple the first non-volatile memory to the second non-volatile memory, and wherein at least one of the multiple bit lines and the multiple sense lines is usable in both read and write operations of the first non-volatile memory and the second non-volatile memory.

23. An apparatus comprising:

means for receiving first data and receiving second data at a single memory cell that comprises a first non-volatile memory and a second non-volatile memory;

means for storing the first data at a first resistive memory element of the first non -volatile memory; and

means for storing the second data at a second resistive memory element of the second non-volatile memory, wherein each of the first non-volatile memory and the second non-volatile memory is accessible via multiple ports.

24. The apparatus of claim 23, further comprising:

means for reading the first data at the first resistive memory element of the first non-volatile memory; and

means for reading the second data at the second resistive memory element of the second non-volatile memory.

25. The apparatus of claim 23, wherein, when a first read operation is performed with respect to the first resistive memory element, a second read operation is concurrently performed with respect to one of the first resistive memory element or the second resistive memory element.

26. The apparatus of claim 23, wherein, when a read operation is performed with respect to the first resistive memory element, a write operation is concurrently performed with respect to one of the first resistive memory element or the second resistive memory element.

27. The apparatus of claim 23, wherein, when a first write operation is performed with respect to the first resistive memory element, a second write operation is concurrently performed with respect to the second resistive memory element.

28. The apparatus of claim 27, wherein a read operation is performed with respect to the first resistive memory element or the second resistive memory element, the read operation performed concurrently with the first write operation and the second write operation.

29. The apparatus of claim 23, further comprising:

means for applying a bit line voltage to a bit line of a particular port of the multiple ports; and

means for applying a sense line voltage to a sense line of the particular port.

30. A non-transitory computer readable medium storing instructions executable by a computer, the instructions comprising:

instructions that are executable by the computer to receive first data and receive second data at a single memory cell that comprises a first non-volatile memory and a second non-volatile memory;

instructions that are executable by the computer to store the first data at a first resistive memory element of the first non-volatile memory; and

instructions that are executable by the computer to store the second data at a second resistive memory element of the second non-volatile memory, wherein each of the first non-volatile memory and the second non-volatile memory is accessible via multiple ports.

31. The non-transitory computer readable medium of claim 30, wherein the memory cell comprises a spin-torque-transfer magnetoresistive random access memory (STT-MRAM) cell.

32. The non-transitory computer readable medium of claim 30, further comprising:

instructions that are executable by the computer to perform a read operation with respect to one of the first resistive memory element or the second resistive memory element, the read operation performed concurrently with a write operation performed with respect to one of the first resistive memory element or the second resistive memory element.

33. The non-transitory computer readable medium of claim 30, further comprising instructions that are executable by the computer to perform a first write operation with respect to the first resistive memory element and a second write operation with respect to the second resistive memory element.

34. The non-transitory computer readable medium of claim 30, wherein each of the multiple ports is associated with a corresponding bit line and a corresponding sense line.

35. The non-transitory computer readable medium of claim 30, wherein multiple bit lines and multiple sense lines couple the first non-volatile memory to the second non-volatile memory.

36. The non-transitory computer readable medium of claim 30, wherein multiple bit lines and multiple sense lines couple the first non-volatile memory to the second non-volatile memory, and wherein at least one of the multiple bit lines and the multiple sense lines is usable in both read and write operations of the first non-volatile memory and the second non-volatile memory.