Semiconductor memory apparatus
First Claim
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1. A semiconductor memory apparatus comprising:
- a resistive memory cell;
a first data transmission unit configured to control an amount of current for the resistive memory cell according to a voltage level of a selection signal;
a data sensing unit configured to sense a first output voltage formed by a sensing current supplied to the resistive memory cell through the first data transmission unit, based on a reference voltage, and output data having a value corresponding to the sensing result;
a dummy memory cell comprising first and second resistors coupled in parallel to each other and having first and second is resistance values, respectively; and
a second data transmission unit configured to control an amount of current for the dummy memory cell according to the voltage level of the selection signal and output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage,wherein the reference voltage has a level in accordance with an intermediate value between the first resistance value and the second resistance value, and the sensing current.
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Abstract
A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.
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Citations
5 Claims
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1. A semiconductor memory apparatus comprising:
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a resistive memory cell; a first data transmission unit configured to control an amount of current for the resistive memory cell according to a voltage level of a selection signal; a data sensing unit configured to sense a first output voltage formed by a sensing current supplied to the resistive memory cell through the first data transmission unit, based on a reference voltage, and output data having a value corresponding to the sensing result; a dummy memory cell comprising first and second resistors coupled in parallel to each other and having first and second is resistance values, respectively; and a second data transmission unit configured to control an amount of current for the dummy memory cell according to the voltage level of the selection signal and output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage, wherein the reference voltage has a level in accordance with an intermediate value between the first resistance value and the second resistance value, and the sensing current. - View Dependent Claims (2, 3, 4, 5)
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Specification