Conversion circuit for converting complex analog signal into digital representation

• US 8,867,671 B2
• Filed: 06/13/2011
• Issued: 10/21/2014
• Est. Priority Date: 06/15/2010
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Strandberg, Roland, Sunstrm, Lars
• Primary Examiner(s): Fan, Chieh M
• Assistant Examiner(s): Koeth, Michelle M
• Application Number:
  US13/702,768
• Publication Number:
  US 20130155748A1
• Time in Patent Office: 1,226 Days
• Field of Search: 455/323, 455/130, 455/302, 455/296, 455313-315, 455/168.1, 455/199.1, 455/189.1, 455/150.1, 455/188.1, 331/45, 375/340, 375/342, 375/316
• US Class Current: 375/340
• CPC Class Codes: H02M 5/02 without intermediate conversion into dc
• CPC Class Codes: H03D 2200/0086 Reduction or prevention of harmonic frequencies
• CPC Class Codes: H03D 3/007 by converting the oscillations into two quadrature related signals H03D3/245 takes precedence
• CPC Class Codes: H03D 7/1466 Passive mixer arrangements
• CPC Class Codes: H03D 7/1483 comprising components for selecting a particular frequency component of the output
• CPC Class Codes: H03D 7/1491 Arrangements to linearise a transconductance stage of a mixer arrangement
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H04B 1/0032 with analogue quadrature frequency conversion to and from the baseband quadrature modulators and demodulators per se H03D3/007, H03C3/40
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A conversion circuit (20) for converting a complex analog input signal having an in-phase, I, component and a quadrature-phase, Q, component resulting from frequency down conversion of a radio-frequency, RF, signal (X_RF) to a frequency band covering 0 Hz into a digital representation is disclosed. It comprises a channel-selection filter unit (40) arranged to filter the complex analog input signal, thereby generating a channel-filtered I and Q components, and one or more processing units (53, 53a-b). Each processing unit comprises four mixers (60-75) for generating a first and a second frequency-translated I component and a first and a second channel-filtered Q component based on two LO signals with equal LO frequency and a 90° mutual phase shift. Furthermore, each processing unit comprises a combiner unit (85, 120) for generating a first, a second, a third, and a fourth combined signal proportional to sums and differences between said frequency translated I and Q components. The first and the fourth combined signals form a first complex signal, and the second and the third combined signals form a second complex signal. Each processing unit further comprises four ADCs (110a-d, 115a-d) for providing digital representations of the first complex signal and the second complex signal for forming said digital representation of the analog complex input signal. A related radio receiver circuit and a related electronic apparatus are also disclosed.

Claims

1. A conversion circuit for converting a complex analog input signal having an in-phase (I) component and a quadrature-phase (Q) component resulting from frequency down conversion of a radio frequency (RF) signal to a frequency band covering 0 Hz into a digital representation, the conversion circuit comprising:

a channel selection filter configured to filter the complex analog input signal, thereby generating a channel-filtered I component and a channel-filtered Q component, wherein the channel selection filter has a passband that covers 0 Hz; and

one or more processing circuits, each comprising;

a first mixer arranged to mix the channel-filtered I component with a first local-oscillator (LO) signal to generate a first frequency-translated I component;

a second mixer arranged to mix the channel-filtered I component with a second LO signal to generate a second frequency-translated I component;

a third mixer arranged to mix the channel-filtered Q component with the first LO signal to generate a first frequency-translated Q component;

a fourth mixer arranged to mix the channel-filtered Q component with the second LO signal to generate a second frequency-translated Q component; and

a combiner circuit configured to generate;

a first combined signal proportional to a sum of the first frequency translated I component and the second frequency-translated Q component;

a second combined signal proportional to a difference between the first frequency translated I component and the second frequency-translated Q component;

a third combined signal proportional to a sum of the second frequency-translated I component and the first frequency-translated Q-component; and

a fourth combined signal proportional to a difference between the first frequency-translated Q component and the second frequency-translated I component;

wherein the first and the fourth combined signals form a first complex signal;

wherein the second and the third combined signals form a second complex signal; and

a first analog-to-digital converter (ADC), a second ADC, a third ADC, and a fourth ADC configured to provide digital representations of the first complex signal and the second complex signal for forming the digital representation of the analog complex input signal;

wherein the first and the second LO signal of a given processing circuit have a common LO frequency associated with the processing circuit and a mutual 90°

phase shift;

wherein each of the first mixer, the second mixer, the third mixer, and the fourth mixer are implemented with a switchable resistor network operatively connected to an input circuit of at least one of the first ADC, the second ADC, the third ADC, and the fourth ADC; and

wherein a resistance of the switchable resistor network is switchably variable in response to either;

the first LO signal for the first and the third mixer;

or

the second LO signal for the second and the fourth mixer.

2. The conversion circuit of claim 1, wherein the first mixer, the second mixer, the third mixer, and the fourth mixer are harmonic rejection mixers.

3. The conversion circuit of claim 1:

wherein the combiner circuit is an analog combiner circuit configured to generate the first combined signal, the second combined signal, the third combined signal, and the fourth combined signal in the analog domain;

wherein the first ADC is arranged to convert the first combined signal to the digital domain;

wherein the second ADC is arranged to convert the second combined signal to the digital domain;

wherein the third ADC is arranged to convert the third combined signal to the digital domain; and

wherein the fourth ADC is arranged to convert the fourth combined signal to the digital domain.

4. The conversion circuit of claim 1:

wherein the combiner circuit is a digital combiner circuit configured to generate the first combined signal, the second combined signal, the third combined signal, and the fourth combined signal in the digital domain based on digital versions of the first frequency-translated I component, the second frequency-translated I component, the first frequency-translated Q component, and the second frequency-translated Q component;

wherein the first ADC is operatively connected to the first mixer and is configured to convert the first frequency-translated I component to the digital version of the first frequency-translated I component;

wherein the second ADC is operatively connected to the second mixer and is configured to convert the second frequency-translated I component to the digital version of the second frequency-translated I component;

wherein the third ADC is operatively connected to the third mixer and is configured to convert the first frequency-translated Q component to the digital version of the first frequency-translated Q component; and

wherein the fourth ADC is operatively connected to the fourth mixer and is configured to convert the second frequency-translated Q component to the digital version of the second frequency-translated Q component.

5. The conversion circuit of claim 1, wherein the switchable resistor network is arranged to provide a constant input resistance to the combination of the switchable resistor network and the input circuit.

6. The conversion circuit of claim 1, wherein the switchable resistor network together with the input circuit forms an active RC integrator.

7. The conversion circuit of claim 1, further comprising a plurality of the processing circuits.

8. The conversion circuit of claim 7, wherein the plurality of processing circuits have mutually different associated LO frequencies.

9. The conversion circuit of claim 1, wherein the channel selection filter comprises:

a first low-pass filter configured filter the I component of the complex analog input signal to generate the channel-filtered I component; and

a second low-pass filter configured to filter the Q component of the complex analog input signal to generate the channel-filtered Q component.

10. The conversion circuit of claim 1, wherein each of the first ADC, the second ADC, the third ADC, and the fourth ADC have a bandwidth that is lower than that of the channel selection filter.

11. A radio receiver circuit comprising:

a quadrature mixer for generating a complex analog input signal by frequency down-conversion of a RF signal to a frequency band covering 0 Hz; and

a conversion circuit for converting the complex analog input signal, which has an in-phase (I) component and a quadrature-phase (Q) component resulting from the frequency down conversion, into a digital representation, the conversion circuit comprising;

a channel selection filter configured to filter the complex analog input signal, thereby generating a channel-filtered I component and a channel-filtered Q component, wherein the channel selection filter has a passband that covers 0 Hz; and

one or more processing circuits, each comprising;

a first mixer arranged to mix the channel-filtered I component with a first local-oscillator (LO) signal to generate a first frequency-translated I component;

a second mixer arranged to mix the channel-filtered I component with a second LO signal to generate a second frequency-translated I component;

a third mixer arranged to mix the channel-filtered Q component with the first LO signal to generate a first frequency-translated Q component;

a fourth mixer arranged to mix the channel-filtered Q component with the second LO signal to generate a second frequency-translated Q component; and

a combiner circuit configured to generate;

a first combined signal proportional to a sum of the first frequency translated I component and the second frequency-translated Q component;

a second combined signal proportional to a difference between the first frequency translated I component and the second frequency-translated Q component;

a third combined signal proportional to a sum of the second frequency-translated I component and the first frequency-translated Q-component; and

a fourth combined signal proportional to a difference between the first frequency-translated Q component and the second frequency-translated I component;

wherein the first and the fourth combined signals form a first complex signal;

wherein the second and the third combined signals form a second complex signal; and

a first analog-to-digital converter (ADC), a second ADC, a third ADC, and a fourth ADC configured to provide digital representations of the first complex signal and the second complex signal for forming the digital representation of the analog complex input signal;

wherein the first and the second LO signal of a processing circuit have a common LO frequency associated with the processing circuit and a mutual 90°

phase shift;

wherein each of the first mixer, the second mixer, the third mixer, and the fourth mixer are implemented with a switchable resistor network operatively connected to an input circuit of at least one of the first ADC, the second ADC, the third ADC, and the fourth ADC; and

wherein a resistance of the switchable resistor network is switchably variable in response to either;

the first LO signal for the first and the third mixer;

or

the second LO signal for the second and the fourth mixer.

12. The radio receiver circuit of claim 11:

wherein the RF signal comprises a number of contiguous frequency bands, each carrying an associated information signal; and

wherein the conversion circuit is configured such that each of the information signals is represented, in its entirety, in the digital representation of one of the first complex signal and the second complex signal of one of the processing circuits of the conversion circuit.

13. The radio receiver circuit of claim 11:

wherein the RF signal comprises a number of contiguous frequency bands, each carrying an associated information signal; and

wherein the conversion circuit is configured such that at least one of the information signals is represented partly in a primary signal of the digital representations of the first complex signal and the second complex signal of one of the processing circuits of the conversion circuit, and partly in a secondary signal of the digital representations of the first complex signal and the second complex signal of one of the processing circuits of the conversion circuit.

14. The radio receiver of claim 13, further comprising recombining circuitry configured to recombine at least one of the information signals from the primary signal and the secondary signal.

15. The radio receiver of claim 14:

wherein the radio receiver circuit is an orthogonal frequency-division multiplexing receiver circuit; and

wherein the recombining circuitry is configured to recombine the at least one of the information signals in the frequency domain.

16. The radio receiver of claim 11, wherein the radio receiver is included in a mobile terminal.

17. The radio receiver of claim 11, wherein the radio receiver is included in a radio base station.

18. The radio receiver claim 11, wherein the switchable resistor network is arranged to provide a constant input resistance to the combination of the switchable resistor network and the input circuit.

19. The radio receiver of claim 11, wherein the switchable resistor network together with the input circuit forms an active RC integrator.