Memory circuit system and method

• US 8,868,829 B2
• Filed: 02/06/2012
• Issued: 10/21/2014
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Rigol, Yaima
• Application Number:
  US13/367,182
• Publication Number:
  US 20120201088A1
• Time in Patent Office: 988 Days
• US Class Current: 711/105
• CPC Class Codes: G11C 11/4063 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.

Claims

1. A method comprising:

presenting a plurality of physical memory circuits to a system as a virtual memory circuit simulated by an interface circuit, wherein the virtual memory circuit has at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits, the at least one characteristic comprising a memory capacity and a command operation period for performing a particular operation on the virtual memory circuit, wherein the command operation period is longer than a latency associated with performing a power-saving operation on any one physical memory circuit of the plurality of physical memory circuits to hide the latency associated with performing the power-saving operation from the system, and wherein the plurality of memory circuits are positioned on a dual in-line memory module (DIMM);

receiving, at the interface circuit, a first command issued from the system to the virtual memory circuit, for performing the particular operation on the virtual memory circuit; and

in response to receiving the first command,

     1) performing the particular operation on a first physical memory circuit of the plurality of physical memory circuits, and

     2) performing, during the particular operation on the first physical memory circuit, a power-saving operation on a portion of the other physical memory circuits of the plurality of physical memory circuits that are identified by the interface circuit as not currently being accessed by the system responsive to a system command issued to the virtual memory circuit.

2. The method of claim 1, wherein the virtual memory circuit has a larger memory capacity than a memory capacity of any one of the physical memory circuits.

3. The method of claim 1, wherein the first command comprises an activate command.

4. The method of claim 3, wherein the activate command comprises a page open command.

5. The method of claim 1, wherein presenting the plurality of physical memory circuits comprises mapping the plurality of physical memory circuits to a single virtual memory bank.

6. The method of claim 1, wherein performing the power-saving operation comprises placing the portion of the other physical memory circuits in a power down mode.

7. The method of claim 6, wherein the power down mode comprises a precharge power down mode.

8. The method of claim 6, wherein the power down mode is during a command operation period of the first physical memory circuit.

9. The method of claim 8, wherein the command operation period is an activate command operation period.

10. The method of claim 8, wherein a length of the command operation period is equal to a row cycle time (tRC).

11. The method of claim 8, wherein the command operation period is longer than a power down entry latency or a power down exit latency of the portion of the other physical memory circuits.

12. The method of claim 1, wherein the at least one characteristic further comprises one or more of a column address strobe (CAS) latency, a row precharge (tRP) latency, or a row address to column address (tRCD) latency.

13. A system comprising:

a plurality of physical memory circuits positioned on a dual in-line memory module (DIMM); and

an interface circuit operable to;

present the plurality of memory circuits to a system as a virtual memory circuit simulated by the interface circuit, wherein the virtual memory circuit has at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits, the at least one characteristic comprising a memory capacity and a command operation period for performing a particular operation on the virtual memo circuit, wherein the command operation period is longer than a latency associated with performing a power-saving operation on any one physical memory circuit of the plurality of physical memory circuits to hide the latency associated with performing the power-saving operation from the system,

receive a first command issued from the memory controller to the virtual memory circuit, for performing the particular operation on the virtual memory circuit, and

in response to receiving the first command,

     1) performing the particular operation on a first physical memory circuit of the plurality of physical memory circuits, and

     2) perform, during the particular operation on the first physical memory circuit, a power-saving operation on a portion of the other physical memory circuits of the plurality of physical memory circuits that are identified by the interface circuit as not currently being accessed by the system responsive to a system command issued to the virtual memory circuit.

14. The system of claim 13, wherein the virtual memory has a larger memory capacity than a memory capacity of any one of the physical memory circuits.

15. The system of claim 13, wherein the first command comprises an activate command.

16. The system of claim 15, wherein the activate command comprises a page open command.

17. The system of claim 13, wherein the interface circuit is operable to map the plurality of physical memory circuits to a single virtual memory bank.

18. The system of claim 13, wherein the interface circuit is operable to perform the power-saving operation by placing the portion of the other physical memory circuits in a power down mode.

19. The system of claim 18, wherein the power down mode comprises a pre-charge power down mode.

20. The system of claim 18, wherein the interface circuit is operable to place the portion of the other physical memory circuits in a power down mode during a command operation period of the first physical memory circuit.

21. The system of claim 20, wherein the command operation period is an activate command operation period.

22. The method of claim 20, wherein a length of the command operation period is equal to a row cycle time (tRC).

23. The system of claim 20, wherein the command operation period is longer than a power down entry latency or a power down exit latency of the portion of the other physical memory circuits.

24. The system of claim 13, wherein the at least one characteristic further comprises one or more of a column address strobe (CAS) latency, a row precharge (tRP) latency, or a row address to column address (tRCD) latency.