Method and apparatus for power control

• US 8,868,949 B2
• Filed: 12/13/2012
• Issued: 10/21/2014
• Est. Priority Date: 01/28/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Carlson, David A., Kessler, Richard E.
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Application Number:
  US13/713,650
• Publication Number:
  US 20130104130A1
• Time in Patent Office: 677 Days
• Field of Search: 713/300, 713/320, 323/907
• US Class Current: 713/320
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y10S 323/907 Temperature compensation of semiconductor

Abstract

Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power.

Claims

1. A method for controlling temperature in a computer chip including multiple processing cores, the method comprising:

operatively coupling a temperature sensor chip external to the computer chip via a diode interface and via a serial connection interface of the computer chip;

tracking the temperature of the computer chip via the serial connection interface by monitoring temperature sensed by the external temperature sensor chip via the diode interface, the diode interface operatively coupled to a thermal diode of the computer chip;

preventing events from being processed in the computer chip to reduce temperature of the computer chip, in an event the monitored temperature exceeds a predetermined threshold;

associating each of the multiple processing cores with a field indicating a maximum power consumption limit for the respective core; and

dynamically adjusting the field associated with at least one of the multiple processing cores in the event the monitored temperature exceeds the predetermined threshold.

2. The method of claim 1 wherein the temperature is a junction temperature of the computer chip.

3. The method of claim 1 wherein preventing events from being processed in the computer chip to reduce temperature of the computer chip includes preventing instructions from being processed.

4. An apparatus for controlling temperature in a computer chip including multiple processing cores each associated with a field indicating a maximum power consumption limit for the respective core, the apparatus comprising:

a diode interface operatively coupled to a thermal diode of the computer chip and to a temperature sensor chip external to the computer chip;

a serial connection interface operatively coupled to the external temperature sensor chip;

a temperature monitor module to track temperature of the computer chip via the serial connection interface by monitoring temperature sensed by the external temperature sensor chip via the diode interface;

a performance reduction module to prevent events from being processed in the computer chip to reduce temperature of the computer chip, in an event the monitored temperature exceeds a predetermined threshold, and to dynamically adjust the field associated with at least one of the multiple processing cores in the event the monitored temperature exceeds the predetermined threshold.

5. The apparatus of claim 4 wherein the temperature is a junction temperature of the computer chip.

6. The apparatus of claim 4 wherein the performance reduction module is configured to prevent events from being processed in the computer chip by preventing instructions from being processed.