Methods for acquiring hyper transport timing and devices thereof

• US 8,868,961 B1
• Filed: 11/06/2009
• Issued: 10/21/2014
• Est. Priority Date: 11/06/2009
• Status: Expired due to Fees

• Current Assignee: F5 Networks, Inc. (F5 Incorporated)
• Original Assignee: F5 Networks, Inc. (F5 Incorporated)
• Inventors: Johnson, C. Stuart, Dabell, Steven D., Steensland, Ronald Lee
• Primary Examiner(s): REHMAN, MOHAMMED H
• Application Number:
  US12/613,806
• Time in Patent Office: 1,810 Days
• Field of Search: 713/400, 713/401
• US Class Current: 713/400
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H04L 25/00 Baseband systems
• CPC Class Codes: H04L 7/00 Arrangements for synchronising receiver with transmitter synchronisation of generators of electric oscillations or pulses H03L7/00
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A method, computer readable medium, system and apparatus that acquires data link timing includes sequentially introducing a delay and sampling data on a link after each sequentially introduced delay. A starting edge of a valid data eye and a trailing edge of the valid data eye during the sequentially introducing the delay and the sampling of the data is determined. The sequentially introduced delay when the starting edge of the valid data eye is detected and a subsequently introduced delay when the trailing edge of the valid data eye is detected are recorded. A bit sampling time that provides the timing for the sampling of data in the valid data eye between the sequentially introduced delay and the subsequently introduced delay is determined. By way of example, an optimum bit sampling time is determined as a mean from the transition of the starting edge of the valid data eye to the trailing edge of the valid data eye. The bit sampling time for the sampling of data is applied and the link is established.

Claims

1. A method for acquiring data link timing, the method comprising:

sequentially introducing a delay and sampling data on a link after each sequentially introduced delay with an application delivery controller;

determining with the application delivery controller a starting edge of a valid data eye and a trailing edge of the valid data eye during the sequentially introducing the delay and sampling data, wherein the determining the starting edge and the trailing edge further comprises performing an error calculation cyclic redundancy check on the sampled data to detect the starting edge of the valid data eye and the trailing edge of the valid data eye;

recording with the application delivery controller the sequentially introduced delay when the starting edge of the valid data eye is detected and a subsequently introduced delay when the trailing edge of the valid data eye is detected;

determining with the application delivery controller a bit sampling time that provides the timing for the sampling of data in the valid data eye between the sequentially introduced delay and the subsequently introduced delay; and

applying the bit sampling time for the sampling of data and establishing the link with the application delivery controller.

2. The method as set forth in claim 1 wherein the bit sampling time comprises a mean of the sequentially introduced delay and the subsequently introduced delay.

3. The method as set forth in claim 1 wherein the bit sampling time is one of greater and less than a mean of the sequentially introduced delay and the subsequently introduced delay.

4. The method as set forth in claim 1 wherein the bit sampling time at a first data rate for the data on the link is used as an initial starting position for determining an updated bit sampling time at a second data rate for the data on the link.

5. The method as set forth in claim 4 wherein the second data rate is higher than the first data rate.

6. The method as set forth in claim 1 wherein the link comprises a Hyper-Transport link.

7. The method as set forth in claim 1 further comprising initially disabling by the application delivery controller transmission of and storing one or more credits to establish the link, wherein the establishing the link further comprises transmitting the one or more stored credits for loading after the bit sampling time is determined.

8. A non-transitory computer readable medium having stored thereon instructions for acquiring data link timing comprising machine executable code which when executed by at least one processor, causes the processor to perform steps comprising:

sequentially introducing a delay and sampling data on a link after each sequentially introduced delay;

determining a starting edge of a valid data eye and a trailing edge of the valid data eye during the sequentially introducing the delay and sampling data, wherein the determining the starting edge and the trailing edge further comprises performing an error calculation cyclic redundancy check on the sampled data to detect the starting edge of the valid data eye and the trailing edge of the valid data eye;

recording the sequentially introduced delay when the starting edge of the valid data eye is detected and a subsequently introduced delay when the trailing edge of the valid data eye is detected;

determining a bit sampling time that provides the timing for the sampling of data in the valid data eye between the sequentially introduced delay and the subsequently introduced delay; and

applying the bit sampling time for the sampling of the data and establishing the link.

9. The medium as set forth in claim 8 wherein the bit sampling time comprises a mean of the sequentially introduced delay and the subsequently introduced delay.

10. The medium as set forth in claim 8 wherein the bit sampling time is one of greater and less than a mean of the sequentially introduced delay and the subsequently introduced delay.

11. The medium as set forth in claim 8 wherein the bit sampling time at a first data rate for the data on the link is used as an initial starting position for determining an updated bit sampling time at a second data rate for the data on the link.

12. The medium as set forth in claim 11 wherein the second data rate is higher than the first data rate.

13. The medium as set forth in claim 8 wherein the link comprises a Hyper-Transport link.

14. The medium as set forth in claim 8 further comprising initially disabling transmission of and storing one or more credits to establish the link, wherein the establishing the link further comprises transmitting the one or more stored credits for loading after the bit sampling time is determined.

15. A Hyper-Transport timing acquisition system comprising:

a data tap management system in an application delivery controller that sequentially introduces a delay and samples data on a link after each sequentially introduced delay;

a timing acquisition processing system in the application delivery controller that determines a start of a stable region and an end of the stable region during the sequentially introduced delay and the sample of the data by performing an error calculation cyclic redundancy check on the sampled data to detect the start and the end of the stable region, records the sequentially introduced delay when the start of the stable region is detected and a subsequently introduced delay when the end of the stable region is detected, determines an acquired delay that provides the timing for the sampling of data in the stable region between the sequentially introduced delay and the subsequently introduced delay and applies the acquired delay for the sampling of the data and establishes the link with the application delivery controller.

16. The system as set forth in claim 15 wherein the timing acquisition processing system in the application delivery controller determines the acquired delay from a mean of the sequentially introduced delay and the subsequently introduced delay.

17. The system as set forth in claim 15 wherein the timing acquisition processing system in the application delivery controller determines the acquired delay to be one of greater and less than a mean of the sequentially introduced delay and the subsequently introduced delay.

18. The system as set forth in claim 15 wherein the timing acquisition processing system in the application delivery controller uses the acquired delay at a first transmitted frequency for the data on the link as an initial starting position for the data tap for determining an updated acquired delay at a second transmitted frequency for the data on the link.

19. The system as set forth in claim 18 wherein the second transmitted frequency is higher than the first transmitted frequency.

20. The system as set forth in claim 15 wherein the link comprises a Hyper-Transport link.

21. The system as set forth in claim 15 wherein the timing acquisition processing system initially disables transmission of and stores one or more credits to establish the link, wherein the timing acquisition processing system establishes the link by transmitting the one or more stored credits for loading after the acquired delay is determined.

22. An application delivery controller apparatus comprising:

one or more host system processors;

a host system memory coupled to the one or more host system processors;

a network interface unit coupled to the one or more host system processors and the host system memory via at least one bus, at least one of the network interface unit configured to implement and the one or more host system processors configured to execute programmed instructions stored in the host memory system comprising;

sequentially introducing a delay and sampling data on the bus after each sequentially introduced delay;

determining a starting edge of a valid data eye and a trailing edge of the valid data eye during the sequentially introducing the delay and sampling data, wherein the determining the starting edge and the trailing edge further comprises performing an error calculation cyclic redundancy check on the sampled data to detect the starting edge of the valid data eye and the trailing edge of the valid data eye;

recording the sequentially introduced delay when the starting edge of the valid data eye is detected and a subsequently introduced delay when the trailing edge of the valid data eye is detected;

determining a bit sampling time that provides the timing for the sampling of data in the valid data eye between the sequentially introduced delay and the subsequently introduced delay; and

applying the bit sampling time for the sampling of the data and establishing data communications over the bus.

23. The apparatus as set forth in claim 22 wherein the bit sampling time comprises a mean of the sequentially introduced delay and the subsequently introduced delay.

24. The apparatus as set forth in claim 22 wherein the bit sampling time is one of greater and less than a mean of the sequentially introduced delay and the subsequently introduced delay.

25. The apparatus as set forth in claim 22 wherein the bit sampling time at a first data rate for the data on the link is used as an initial starting position for determining an updated bit sampling time at a second data rate for the data on the link.

26. The apparatus as set forth in claim 25 wherein the second data rate is higher than the first data rate.

27. The apparatus as set forth in claim 22 wherein the link comprises a Hyper-Transport link.

28. The apparatus as set forth in claim 22 further comprising initially disabling transmission of and storing one or more credits to establish the link, wherein the establishing the link further comprises transmitting the one or more stored credits for loading after the bit sampling time is determined.