Method for the translation of programs for reconfigurable architectures

• US 8,869,121 B2
• Filed: 07/07/2011
• Issued: 10/21/2014
• Est. Priority Date: 08/16/2001
• Status: Expired due to Fees

• Current Assignee: PACT XPP Schweiz AG
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, May, Frank, Nckel, Armin
• Primary Examiner(s): DAO, THUY CHAN
• Application Number:
  US13/177,820
• Publication Number:
  US 20110271264A1
• Time in Patent Office: 1,202 Days
• US Class Current: 717/140
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

Data processing using multidimensional fields is described along with methods for advantageously using high-level language codes.

Claims

1. A computer-implemented method for compiling high-level software programs into instruction level parallel code, comprising:

generating a code graph, line by line, wherein a line, p, comprises one or more of nodes that are executed within one clock unit, a node comprising one or more operations;

in a first analysis, analyzing a line, by a computer processor, for nodes that may be executed simultaneously, the analysis determining a;

content PAR{ }, each term in PAR{ } is process simultaneously;

in a second analysis, analyzing, by the processor, a line for nodes that may be sequentially executable from a previous line to yield a content VEC{ }, each term in VEC{ } is processed in succession; and

determining the configuration of a next line depending on the first and second analyses, wherein a value of PAR(p), PAR(p) comprising the number of nodes that may be executed simultaneously at a certain stage (p), being less than (p) in a given line determines that the number of nodes in the next line is (p);

wherein if (p)is no less than PAR(p), determining that the number of nodes to be executed in the next line the number of node defined by PAR{ }; and

wherein a value of VEC being less than 1 determines that a node in the next line not be successive.

2. The method according to claim 1, wherein the partitioning includes mapping of parts of the code graph onto sequential processing units.

3. The method according to claim 2, wherein at least some of the sequential processing units are horizontally connected and operate on commonly received data input.

4. The method according to any one of claims 2 and 3, wherein at least some of the sequential processing units are vertically connected, and each of at least one of the sequential processing units operates on data received from at least one other of the sequential processing units.

5. The method according to claim 4, wherein code for a reconfigurable processor is produced by the method.

6. The method according to claim 4, wherein code for a field programmable gate array (FPGA) is produced by the method.

7. The method according to claim 4, wherein code for a central processing unit (CPU) is produced by the method.

8. The method according to claim 4, wherein code for a parallel processor system is produced by the method.

9. The method according to any one of claims 1 to 3, wherein code for a reconfigurable processor is produced by the method.

10. The method according to any one of claims 1 to 3, wherein code for a field programmable gate array (FPGA) is produced by the method.

11. The method according to any one of claims 1 to 3, wherein code for a central processing unit (CPU) is produced by the method.

12. The method according to any one of claims 1 to 3, wherein code for a parallel processor system is produced by the method.

13. The method according to claim 1, wherein all of the instructions of one of the levels of the code graph are separate from all of the instructions on each of the other levels of the code graph.