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Multi-threaded processor with deferred thread output control

  • US 8,869,147 B2
  • Filed: 05/31/2006
  • Issued: 10/21/2014
  • Est. Priority Date: 05/31/2006
  • Status: Active Grant
First Claim
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1. A multi-threaded processor comprising:

  • a thread scheduler configured to track a sequence in which a plurality of threads is received at an input interface of the multi-threaded processor;

    an internal memory buffer configured to temporarily store thread results corresponding to the plurality of received threads; and

    a processing unit coupled to the thread scheduler and the internal memory buffer, the processing unit configured to;

    process the plurality of threads out of sequence to obtain a plurality of corresponding thread results, andstore the plurality of thread results in the internal memory buffer,wherein the thread scheduler is configured to cause the plurality of thread results stored in the internal memory buffer to be outputted from the multi-threaded processor in the sequence in which the corresponding threads were received by the multi-threaded processor.

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