Multi-threaded processor with deferred thread output control
First Claim
1. A multi-threaded processor comprising:
- a thread scheduler configured to track a sequence in which a plurality of threads is received at an input interface of the multi-threaded processor;
an internal memory buffer configured to temporarily store thread results corresponding to the plurality of received threads; and
a processing unit coupled to the thread scheduler and the internal memory buffer, the processing unit configured to;
process the plurality of threads out of sequence to obtain a plurality of corresponding thread results, andstore the plurality of thread results in the internal memory buffer,wherein the thread scheduler is configured to cause the plurality of thread results stored in the internal memory buffer to be outputted from the multi-threaded processor in the sequence in which the corresponding threads were received by the multi-threaded processor.
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Accused Products
Abstract
A multi-threaded processor is provided that internally reorders output threads thereby avoiding the need for an external output reorder buffer. The multi-threaded processor writes its thread results back to an internal memory buffer to guarantee that thread results are outputted in the same order in which the threads are received. A thread scheduler within the multi-threaded processor manages thread ordering control to avoid the need for an external reorder buffer. A compiler for the multi-threaded processor converts instructions that would normally send processed results directly to an external reorder buffer so that the processed thread results are instead sent to the internal memory buffer of the multi-threaded processor.
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Citations
20 Claims
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1. A multi-threaded processor comprising:
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a thread scheduler configured to track a sequence in which a plurality of threads is received at an input interface of the multi-threaded processor; an internal memory buffer configured to temporarily store thread results corresponding to the plurality of received threads; and a processing unit coupled to the thread scheduler and the internal memory buffer, the processing unit configured to; process the plurality of threads out of sequence to obtain a plurality of corresponding thread results, and store the plurality of thread results in the internal memory buffer, wherein the thread scheduler is configured to cause the plurality of thread results stored in the internal memory buffer to be outputted from the multi-threaded processor in the sequence in which the corresponding threads were received by the multi-threaded processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A multi-threaded processor comprising:
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means for tracking a sequence in which a plurality of threads is received at an input interface of the multi-threaded processor; means for processing the plurality of threads out of sequence to obtain a plurality of corresponding results; means for storing the plurality of results in an internal memory buffer; and means for causing the plurality of stored results to be outputted from the internal memory buffer in the sequence in which the corresponding threads were received by the multi-threaded processor. - View Dependent Claims (11, 12)
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13. A method for reordering the sequence of a plurality of thread results within a multi-threaded processor, comprising:
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tracking a sequence in which a plurality of threads is received by the multi-threaded processor; processing the plurality of threads out of sequence on a single core to obtain a plurality of corresponding results; storing the plurality of results in an internal memory buffer; and sending out the plurality of stored results stored in the internal memory buffer from the multi-threaded processor in the sequence in which the corresponding threads were received by the multi-threaded processor. - View Dependent Claims (14, 15)
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16. A graphics processor comprising:
a multi-threaded processor having a core, the core configured to; track a sequence in which a plurality of threads including pixel data is received from a first application; store the plurality of received threads in an internal memory buffer; process the plurality of threads in a different sequence than the sequence in which the plurality of threads were received according to an order defined by flow control instructions associated with the plurality of threads to obtain a plurality of corresponding results; store the plurality of results in the internal memory buffer; and output the plurality of results to the first application from the internal memory buffer in the sequence in which the corresponding threads were received from the application. - View Dependent Claims (17)
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18. A non-transitory computer-readable medium for use in reordering the sequence of a plurality thread results within a multi-threaded processor, the medium comprising instructions stored thereon to cause the multi-threaded processor to:
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track a sequence in which a plurality of threads is received by the multi-threaded processor; process the plurality of threads out of sequence on a single core to obtain a plurality of corresponding results; store the plurality of results in an internal memory buffer; and send out the plurality of stored results from the internal memory buffer in the sequence in which the corresponding threads were received by the multi-threaded processor. - View Dependent Claims (19, 20)
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Specification